455 lines
15 KiB
C
455 lines
15 KiB
C
//*****************************************************************************
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//
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// am_hal_wdt.c
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//! @file
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//!
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//! @brief Hardware abstraction layer for the Watchdog Timer module.
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//!
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//! @addtogroup wdt2 Watchdog Timer (WDT)
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//! @ingroup apollo2hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Adjacency check
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//
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// This is related to the timer read workaround. This macro checks to see if
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// the two supplied count values are within one "tick" of eachother. It should
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// still pass in the event of a timer rollover. The "B" read is assumed to
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// follow the "A" read. The macro returns "TRUE" when the adjacent timer reads
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// can be used.
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//
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//*****************************************************************************
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#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0))
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//*****************************************************************************
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//
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//! @brief Configure the watchdog timer.
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//!
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//! @param psConfig - pointer to a configuration structure containing the
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//! desired watchdog settings.
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//!
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//! This function will set the watchdog configuration register based on the
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//! user's desired settings listed in the structure referenced by psConfig. If
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//! the structure indicates that watchdog interrupts are desired, this function
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//! will also set the interrupt enable bit in the configuration register.
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//!
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//! @note In order to actually receive watchdog interrupt and/or watchdog reset
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//! events, the caller will also need to make sure that the watchdog interrupt
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//! vector is enabled in the ARM NVIC, and that watchdog resets are enabled in
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//! the reset generator module. Otherwise, the watchdog-generated interrupt and
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//! reset events will have no effect.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_wdt_init(const am_hal_wdt_config_t *psConfig)
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{
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uint32_t ui32ConfigVal;
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uint16_t ui16IntCount, ui16ResetCount;
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bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET;
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bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT;
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//
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// Read the desired settings from the psConfig structure.
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//
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ui16IntCount = psConfig->ui16InterruptCount;
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ui16ResetCount = psConfig->ui16ResetCount;
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//
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// Write the interrupt and reset count values to a temporary variable.
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//
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// Accept the passed Config value, but clear the Counts that we are about to set.
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ui32ConfigVal = psConfig->ui32Config & ~(AM_REG_WDT_CFG_INTVAL_M | AM_REG_WDT_CFG_RESVAL_M);
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ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_INTVAL, ui16IntCount);
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ui32ConfigVal |= AM_WRITE_SM(AM_REG_WDT_CFG_RESVAL, ui16ResetCount);
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//
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// If interrupts should be enabled, set the appropriate bit in the
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// temporary variable. Also, enable the interrupt in INTEN register in the
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// watchdog module.
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//
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if ( bInterruptEnabled )
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{
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//
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// Enable the watchdog interrupt if the configuration calls for them.
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//
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AM_REGn(WDT, 0, INTEN) |= AM_REG_WDT_INTEN_WDT_M;
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}
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else
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{
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//
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// Disable the watchdog interrupt if the configuration doesn't call for
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// watchdog interrupts.
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//
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AM_REGn(WDT, 0, INTEN) &= ~AM_REG_WDT_INTEN_WDT_M;
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}
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//
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// If resets should be enabled, set the appropriate bit in the temporary
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// variable.
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//
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if ( bResetEnabled )
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{
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//
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// Also enable watchdog resets in the reset module.
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//
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AM_REG(RSTGEN, CFG) |= AM_REG_RSTGEN_CFG_WDREN_M;
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}
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else
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{
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//
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// Disable watchdog resets in the reset module.
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//
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AM_REG(RSTGEN, CFG) &= ~AM_REG_RSTGEN_CFG_WDREN_M;
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}
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//
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// Check for a user specified clock select. If none specified then
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// set 128Hz.
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//
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if ( !(psConfig->ui32Config & AM_REG_WDT_CFG_CLKSEL_M) )
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{
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ui32ConfigVal |= AM_REG_WDT_CFG_CLKSEL_128HZ;
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}
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//
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// Write the saved value to the watchdog configuration register.
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//
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AM_REGn(WDT, 0, CFG) = ui32ConfigVal;
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}
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//*****************************************************************************
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//
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//! @brief Starts the watchdog timer.
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//!
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//! Enables the watchdog timer tick using the 'enable' bit in the watchdog
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//! configuration register. This function does not perform any locking of the
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//! watchdog timer, so it can be disabled or reconfigured later.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_wdt_start(void)
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{
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//
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// Make sure the watchdog timer is in the "reset" state, and then set the
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// enable bit to start counting.
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//
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AM_REGn(WDT, 0, CFG) |= AM_REG_WDT_CFG_WDTEN_M;
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AM_REGn(WDT, 0, RSTRT) |= AM_REG_WDT_RSTRT_RSTRT_KEYVALUE;
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}
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//*****************************************************************************
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//
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//! @brief Stops the watchdog timer.
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//!
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//! Disables the watchdog timer tick by clearing the 'enable' bit in the
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//! watchdog configuration register.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_wdt_halt(void)
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{
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//
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// Clear the watchdog enable bit.
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//
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AM_REGn(WDT, 0, CFG) &= ~AM_REG_WDT_CFG_WDTEN_M;
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}
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//*****************************************************************************
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//
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//! @brief Locks the watchdog configuration and starts the watchdog timer.
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//!
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//! This function sets the watchdog "lock" register, which prevents software
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//! from re-configuring the watchdog. This action will also set the enable bit
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//! for the watchdog timer, so it will start counting immediately.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_wdt_lock_and_start(void)
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{
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//
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// Write the 'key' value to the watchdog lock register.
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//
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AM_REGn(WDT, 0, LOCK) = AM_REG_WDT_LOCK_LOCK_KEYVALUE;
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}
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//*****************************************************************************
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//
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//! @brief Read the state of the wdt interrupt status.
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//!
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//! @param bEnabledOnly - return the status of only the enabled interrupts.
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//!
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//! This function extracts the interrupt status bits and returns the enabled or
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//! raw based on bEnabledOnly.
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//!
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//! @return WDT interrupt status.
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//
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//*****************************************************************************
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uint32_t
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am_hal_wdt_int_status_get(bool bEnabledOnly)
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{
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if (bEnabledOnly)
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{
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uint32_t u32RetVal = AM_REG(WDT, INTSTAT);
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return u32RetVal & AM_REG(WDT, INTEN);
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}
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else
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{
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return AM_REG(WDT, INTSTAT);
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}
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}
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//*****************************************************************************
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//
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//! @brief Set the state of the wdt interrupt status bit.
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//!
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//! This function sets the interrupt bit.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_wdt_int_set(void)
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{
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AM_REG(WDT, INTSET) = AM_REG_WDT_INTSET_WDT_M;
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}
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//*****************************************************************************
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//
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//! @brief Clear the state of the wdt interrupt status bit.
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//!
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//! This function clear the interrupt bit.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_wdt_int_clear(void)
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{
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AM_REGn(WDT, 0, INTCLR) = AM_REG_WDT_INTCLR_WDT_M;
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}
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//*****************************************************************************
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//
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//! @brief Enable the wdt interrupt.
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//!
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//! This function enable the interrupt.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_wdt_int_enable(void)
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{
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AM_REG(WDT, INTEN) |= AM_REG_WDT_INTSET_WDT_M;
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}
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//*****************************************************************************
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//
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//! @brief Return the enabled WDT interrupts.
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//!
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//! This function returns the enabled WDT interrupts.
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//!
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//! @return enabled WDT interrupts.
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//
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//*****************************************************************************
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uint32_t
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am_hal_wdt_int_enable_get(void)
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{
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return AM_REG(WDT, INTEN);
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}
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//*****************************************************************************
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//
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//! @brief Disable the wdt interrupt.
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//!
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//! This function disablee the interrupt.
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//!
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//! @return None
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//
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//*****************************************************************************
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void
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am_hal_wdt_int_disable(void)
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{
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AM_REG(WDT, INTEN) &= ~AM_REG_WDT_INTSET_WDT_M;
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}
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//*****************************************************************************
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//
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// Static function for reading the WDT counter value.
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//
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//*****************************************************************************
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#if defined(__GNUC_STDC_INLINE__)
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__attribute__((naked))
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static
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void
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back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register)
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{
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// pui32Array[] is a pointer to a 3 word data array provided by the caller.
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// pui32Register = address of the timer to be read.
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__asm
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(
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// Do 3 back-to-back reads of the register
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" ldr r2, [r1, #0]\n" // Get counter register value
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" ldr r3, [r1, #0]\n" // Get counter register value again
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" ldr r1, [r1, #0]\n" // Get counter register value for a third time
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" str r2, [r0, #0]\n" // Store register value to variable
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" str r3, [r0, #4]\n" // Store register value to variable
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" str r1, [r0, #8]\n" // Store register value to variable
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" bx lr\n"
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);
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}
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#elif defined(__ARMCC_VERSION)
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__asm static uint32_t
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back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register)
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{
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ldr r2, [r1, #0] // Get TMRn register value
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ldr r3, [r1, #0] // Get TMRn register value again
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ldr r1, [r1, #0] // Get TMRn register value for a third time
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str r2, [r0, #0] // Store register value to variable
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str r3, [r0, #4] // Store register value to variable
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str r1, [r0, #8] // Store register value to variable
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bx lr
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}
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma diag_suppress = Pe940 // Suppress IAR compiler warning about missing
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// return statement on a non-void function
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__stackless static uint32_t
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back2back_read_asm(uint32_t *pui32Array, uint32_t *pui32Register)
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{
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__asm(" ldr r2, [r1, #0]"); // Get TMRn register value
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__asm(" ldr r3, [r1, #0]"); // Get TMRn register value again
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__asm(" ldr r1, [r1, #0]"); // Get TMRn register value for a third time
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__asm(" str r2, [r0, #0]"); // Store register value to variable
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__asm(" str r3, [r0, #4]"); // Store register value to variable
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__asm(" str r1, [r0, #8]"); // Store register value to variable
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__asm(" bx lr");
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}
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#pragma diag_default = Pe940 // Restore IAR compiler warning
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#endif
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//*****************************************************************************
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//
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//! @brief Get the wdt counter value.
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//!
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//! This function reads the current value of watch dog timer counter register.
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//!
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//! WARNING caller is responsible for masking interrutps before calling this
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//! function.
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//!
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//! @return None
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//
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//*****************************************************************************
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uint32_t
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am_hal_wdt_counter_get(void)
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{
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uint32_t ui32Values[3] = {0};
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uint32_t ui32Value;
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//
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// First, go read the value from the counter register 3 times
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// back to back in assembly language.
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//
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back2back_read_asm(ui32Values, (uint32_t *)AM_REG_WDTn(0));
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//
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// Now, we'll figure out which of the three values is the correct time.
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//
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if (ui32Values[0] == ui32Values[1])
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{
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//
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// If the first two values match, then neither one was a bad read.
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// We'll take this as the current time.
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//
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ui32Value = ui32Values[1];
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}
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else
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{
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//
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// If the first two values didn't match, then one of them might be bad.
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// If one of the first two values is bad, then the third one should
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// always be correct. We'll take the third value as the correct count.
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//
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ui32Value = ui32Values[2];
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//
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// If all of the statements about the architecture are true, the third
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// value should be correct, and it should always be within one count of
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// either the first or the second value.
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//
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// Just in case, we'll check against the previous two values to make
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// sure that our final answer was reasonable. If it isn't, we will
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// flag it as a "bad read", and fail this assert statement.
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//
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// This shouldn't ever happen, and it hasn't ever happened in any of
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// our tests so far.
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//
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am_hal_debug_assert_msg((adjacent(ui32Values[1], ui32Values[2]) ||
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adjacent(ui32Values[0], ui32Values[2])),
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"Bad CDT read");
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}
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return ui32Value;
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}
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//*****************************************************************************
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//
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// End Doxygen group.
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//! @}
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//
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//*****************************************************************************
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