230 lines
4.4 KiB
C
230 lines
4.4 KiB
C
/*
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* File : cpuport.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#define ICACHE_MASK (rt_uint32_t)(1 << 12)
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#define DCACHE_MASK (rt_uint32_t)(1 << 2)
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extern void machine_reset(void);
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extern void machine_shutdown(void);
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#if defined(__GNUC__) || defined(__ICCARM__)
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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__asm volatile(\
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"orr r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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: "r"(bit) \
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: "memory");
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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__asm volatile(\
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"mrc p15,0,r0,c1,c0,0\n\t" \
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"bic r0,r0,%0\n\t" \
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"mcr p15,0,r0,c1,c0,0" \
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: \
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: "r"(bit) \
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: "memory");
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}
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#endif
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#if defined(__CC_ARM)
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rt_inline rt_uint32_t cp15_rd(void)
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{
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rt_uint32_t i;
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__asm volatile
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{
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mrc p15, 0, i, c1, c0, 0
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}
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return i;
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}
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rt_inline void cache_enable(rt_uint32_t bit)
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{
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rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, bit
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mcr p15, 0, value, c1, c0, 0
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}
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}
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rt_inline void cache_disable(rt_uint32_t bit)
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{
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rt_uint32_t value;
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__asm volatile
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, bit
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mcr p15, 0, value, c1, c0, 0
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}
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}
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#endif
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/**
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* enable I-Cache
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*
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*/
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void rt_hw_cpu_icache_enable()
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{
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cache_enable(ICACHE_MASK);
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}
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/**
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* disable I-Cache
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*
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*/
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void rt_hw_cpu_icache_disable()
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{
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cache_disable(ICACHE_MASK);
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}
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/**
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* return the status of I-Cache
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*
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*/
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rt_base_t rt_hw_cpu_icache_status()
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{
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return (cp15_rd() & ICACHE_MASK);
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}
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/**
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* enable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_enable()
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{
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cache_enable(DCACHE_MASK);
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}
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/**
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* disable D-Cache
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*
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*/
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void rt_hw_cpu_dcache_disable()
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{
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cache_disable(DCACHE_MASK);
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}
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/**
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* return the status of D-Cache
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*
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*/
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rt_base_t rt_hw_cpu_dcache_status()
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{
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return (cp15_rd() & DCACHE_MASK);
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}
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/**
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* reset cpu by dog's time-out
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*
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*/
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void rt_hw_cpu_reset()
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{
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rt_kprintf("Restarting system...\n");
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machine_reset();
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while (1); /* loop forever and wait for reset to happen */
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/* NEVER REACHED */
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}
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/**
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* shutdown CPU
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*
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*/
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void rt_hw_cpu_shutdown()
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{
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rt_uint32_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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machine_shutdown();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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#ifdef RT_USING_CPU_FFS
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/**
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* This function finds the first bit set (beginning with the least significant bit)
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* in value and return the index of that bit.
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*
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* Bits are numbered starting at 1 (the least significant bit). A return value of
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* zero from any of these functions means that the argument was zero.
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*
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* @return return the index of the first bit set. If value is 0, then this function
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* shall return 0.
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*/
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#if defined(__CC_ARM)
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int __rt_ffs(int value)
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{
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register rt_uint32_t x;
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if (value == 0)
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return value;
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__asm
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{
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rsb x, value, #0
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and x, x, value
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clz x, x
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rsb x, x, #32
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}
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return x;
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}
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#elif defined(__GNUC__) || defined(__ICCARM__)
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int __rt_ffs(int value)
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{
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return __builtin_ffs(value);
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}
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#endif
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#endif
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/*@}*/
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