614 lines
13 KiB
C
614 lines
13 KiB
C
/*
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* File : drv_clock.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "drv_clock.h"
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int cpu_get_pll_clk(void)
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{
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rt_uint32_t reg;
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int n, k, m, p;
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reg = CCU->pll_cpu_ctrl;
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if (!(reg & (0x01 << 31)))
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return 0;
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p = PLL_CPU_DIV_P(reg) + 1;
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n = PLL_CPU_FACTOR_N(reg) + 1;
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k = PLL_CPU_FACTOR_K(reg) + 1;
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m = PLL_CPU_FACTOR_M(reg) + 1;
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//(24MHz*n*k)/(m*p)
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return (_24MHZ_ * n * k) / (m * p);
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}
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int audio_get_pll_clk(void)
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{
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rt_uint32_t reg;
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unsigned char n, m;
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reg = CCU->pll_audio_ctrl;
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if (!(reg & (0x01 << 31)))
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return 0;
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n = PLL_AUDIO_FACTOR_N(reg) + 1;
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m = PLL_AUDIO_PREDIV_M(reg) + 1;
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//24MHz*n*2/m
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return _24MHZ_ * 2 * n / m;
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}
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int video_get_pll_clk(void)
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{
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rt_uint32_t reg;
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int n, m;
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reg = CCU->pll_video_ctrl;
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if (!(reg & (0x01 << 31)))
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return 0;
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if (reg & PLL_VIDEO_MODE_SEL)
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{
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//(24MHz*n)/m
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n = PLL_VIDEO_FACTOR_N(reg) + 1;
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m = PLL_VIDEO_PREDIV_M(reg) + 1;
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return (_24MHZ_ * n) / m;
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}
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if (reg & PLL_VIDEO_FRAC_CLK_OUT)
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return 270000000;
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else
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return 297000000;
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return 0;
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}
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int ve_get_pll_clk(void)
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{
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rt_uint32_t reg;
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int n, m;
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reg = CCU->pll_ve_ctrl;
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if (!(reg & (0x01 << 31)))
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return 0;
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if (reg & PLL_VE_MODE_SEL)
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{
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//(24MHz*n)/m
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n = PLL_VE_FACTOR_N(reg) + 1;
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m = PLL_VE_PREDIV_M(reg) + 1;
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return (_24MHZ_ * n) / m;
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}
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if (reg & PLL_VE_FRAC_CLK_OUT)
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return 297000000;
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else
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return 270000000;
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return 0;
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}
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int ddr_get_pll_clk(void)
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{
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rt_uint32_t reg;
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int n, k, m;
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reg = CCU->pll_ddr_ctrl;
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if (!(reg & (0x01 << 31)))
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return 0;
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n = PLL_DDR_FACTOR_N(reg) + 1;
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k = PLL_DDR_FACTOR_K(reg) + 1;
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m = PLL_DDR_FACTOR_M(reg) + 1;
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//(24MHz*n*k)/m
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return (_24MHZ_ * n * k) / m;
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}
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int periph_get_pll_clk(void)
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{
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rt_uint32_t reg;
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int n, k;
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reg = CCU->pll_periph_ctrl;
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if (!(reg & (0x01 << 31)))
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return 0;
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n = PLL_PERIPH_FACTOR_N(reg) + 1;
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k = PLL_PERIPH_FACTOR_K(reg) + 1;
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return _24MHZ_ * n * k;
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}
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static int cpu_get_clk_src(void)
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{
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return (CCU->cpu_clk_src >> 16) & 0x3;
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}
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int cpu_get_clk(void)
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{
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rt_uint32_t reg;
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int cpusrc;
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reg = CCU->ahb_apb_hclkc_cfg;
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cpusrc = cpu_get_clk_src();
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if (cpusrc == CLK_PLL_SRC)
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return (cpu_get_pll_clk() / (HCLKC_DIV(reg) + 1));
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else if (cpusrc == CLK_OSC24M_SRC)
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return _24MHZ_ / (HCLKC_DIV(reg) + 1);
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else
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return _32KHZ_ / (HCLKC_DIV(reg) + 1); //猜测 内部32KHz时钟
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return 0;
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}
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int ahb_get_clk(void)
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{
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rt_uint32_t reg;
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int sel, spd;
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reg = CCU->ahb_apb_hclkc_cfg;
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sel = AHB_SRC_SEL(reg);
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if (sel == CLK_PLL_SRC)
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{
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spd = cpu_get_clk();
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return spd / (1 << AHB_CLK_DIV(reg));
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}
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else if (sel == PRE_DIV_SRC)
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{
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spd = periph_get_pll_clk();
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return spd / (AHB_PRE_DIV(reg) + 1) / (1 << AHB_CLK_DIV(reg));
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}
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else if (sel == CLK_OSC24M_SRC)
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return _24MHZ_ / (1 << AHB_CLK_DIV(reg));
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else
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return _32KHZ_ / (1 << AHB_CLK_DIV(reg));
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}
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int apb_get_clk(void)
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{
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rt_uint32_t reg;
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int spd;
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reg = CCU->ahb_apb_hclkc_cfg;
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spd = ahb_get_clk();
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// 0x:/2 10:/4 11:/8
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if (!(APH_CLK_PATIO(reg) & 0x1))
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return spd / 2;
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else
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return spd / (1 << APH_CLK_PATIO(reg));
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}
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static rt_err_t wait_pll_stable(rt_uint32_t base)
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{
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rt_uint32_t rval = 0;
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volatile int time = 0xfff;
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do
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{
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rval = *((volatile rt_uint32_t *)base);
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time--;
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}
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while (time && !(rval & (1 << 28)));
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return !time;
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}
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rt_err_t cpu_set_pll_clk(int clk)
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{
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rt_uint32_t cpu_src;
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int p = 0, k = 1, m = 1, n = 0;
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if (clk == 0)
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return RT_EINVAL;
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if (clk > 1152000000)
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{
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k = 2;
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}
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else if (clk > 768000000)
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{
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k = 3;
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m = 2;
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}
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n = clk / (_24MHZ_ * k / m) - 1;
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cpu_src = (CCU->cpu_clk_src >> 16) & 0x3;
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CCU->cpu_clk_src = CLK_OSC24M_SRC << 16;
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CCU->pll_cpu_ctrl &= ~(0x1 << 31);
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//PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
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CCU->pll_cpu_ctrl = (0x1 << 31) | (m << 0) | (k << 4) | (n << 8) | (p << 16);
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if (wait_pll_stable((rt_uint32_t)(&CCU->pll_cpu_ctrl)))
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return RT_ERROR;
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CCU->cpu_clk_src = cpu_src << 16;
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return RT_EOK;
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}
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rt_err_t audio_set_pll_clk(int clk)
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{
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int n = 0, m = 0;
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int n_temp = clk;
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int m_temp = _24MHZ_ * 2;
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if ((clk > 200000000) || (clk < 20000000))
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return RT_EINVAL;
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if (clk == 0)
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{
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CCU->pll_audio_ctrl &= ~(0x1 << 31);
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return RT_EOK;
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}
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while (n_temp != m_temp)
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{
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if (n_temp > m_temp)
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{
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n_temp = n_temp - m_temp;
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}
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else if (m_temp > n_temp)
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{
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m_temp = m_temp - n_temp;
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}
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}
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n = clk / n_temp;
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m = _24MHZ_ * 2 / m_temp;
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if ((n > 128) || (m > 32) || (clk != (_24MHZ_ * n * 2) / m))
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return RT_ERROR;
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CCU->pll_audio_ctrl &= ~(0x1 << 31);
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n = (n - 1) & 0x7f;
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m = (m - 1) & 0x1f;
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//clk = (24 * n * 2) / m
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CCU->pll_audio_ctrl = (0x1 << 31) | (0x0 << 24) | (n << 8) | m;
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if (wait_pll_stable((rt_uint32_t)(&CCU->pll_audio_ctrl)))
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return RT_ERROR;
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else
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return RT_EOK;
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}
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rt_err_t video_set_pll_clk(int clk)
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{
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int n = 0, m = 0;
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int n_temp = clk;
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int m_temp = _24MHZ_;
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if ((clk > 600000000) || (clk < 30000000))
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return RT_EINVAL;
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if (clk == 0)
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{
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CCU->pll_video_ctrl &= ~(0x1 << 31);
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return RT_EOK;
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}
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while (n_temp != m_temp)
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{
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if (n_temp > m_temp)
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{
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n_temp = n_temp - m_temp;
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}
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else if (m_temp > n_temp)
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{
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m_temp = m_temp - n_temp;
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}
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}
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n = clk / n_temp;
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m = _24MHZ_ / m_temp;
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if ((n > 128) || (m > 16) || (clk != (_24MHZ_ * n) / m))
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return RT_ERROR;
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CCU->pll_video_ctrl &= ~(0x1 << 31);
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n = (n - 1) & 0x7f;
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m = (m - 1) & 0xf;
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//speed = (24*n)/m
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CCU->pll_video_ctrl = (0x1 << 31) | (0x0 << 30) | (0x1 << 24) | (n << 8) | m;
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if (wait_pll_stable((rt_uint32_t)(&CCU->pll_video_ctrl)))
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return RT_ERROR;
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else
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return RT_EOK;
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}
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rt_err_t ve_set_pll_clk(int clk)
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{
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int n = 0, m = 0;
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int n_temp = clk;
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int m_temp = _24MHZ_;
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if ((clk > 600000000) || (clk < 30000000))
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return RT_EINVAL;
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if (clk == 0)
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{
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CCU->pll_ve_ctrl &= ~(0x1 << 31);
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return RT_EOK;
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}
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while (n_temp != m_temp)
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{
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if (n_temp > m_temp)
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{
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n_temp = n_temp - m_temp;
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}
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else if (m_temp > n_temp)
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{
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m_temp = m_temp - n_temp;
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}
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}
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n = clk / n_temp;
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m = _24MHZ_ / m_temp;
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if ((n > 128) || (m > 16) || (clk != (_24MHZ_ * n) / m))
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return RT_ERROR;
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CCU->pll_ve_ctrl &= ~(0x1 << 31);
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n = (n - 1) & 0x7f;
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m = (m - 1) & 0xf;
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//clk = (24 * n) / m
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CCU->pll_ve_ctrl = (0x1 << 31) | (0x1 << 24) | (n << 8) | m;
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if (wait_pll_stable((rt_uint32_t)(&CCU->pll_ve_ctrl)))
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return RT_ERROR;
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else
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return RT_EOK;
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}
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rt_err_t periph_set_pll_clk(int clk)
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{
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rt_uint32_t clk_src;
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rt_uint32_t temp_data;
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int n = 0, k = 0;
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if ((clk > 1800000000) || (clk < 200000000) || (clk == 0) || (clk % _24MHZ_ != 0))
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return RT_EINVAL;
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n = clk / _24MHZ_;
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for (k = 2; ((n > 32) || (k < 5)); k++)
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{
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if ((n % k) != 0)
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n /= k;
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}
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if ((n > 32) || (k > 4) || (clk != (_24MHZ_ * n * k)))
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return RT_ERROR;
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temp_data = CCU->ahb_apb_hclkc_cfg;
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clk_src = (temp_data >> 12) & 0x3;
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temp_data &= ~(0x3 << 12);
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temp_data |= (CLK_PLL_SRC << 12);
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CCU->ahb_apb_hclkc_cfg = temp_data;
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CCU->pll_periph_ctrl &= ~(0x1 << 31);
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n = (n - 1) & 0x1f;
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k = (k - 1) & 0x3;
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//clk = 24 * n *k
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CCU->pll_periph_ctrl = (0x1 << 31) | (0x1 << 18) | (n << 8) | (k << 4) || (0x1);
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if (wait_pll_stable((rt_uint32_t)(&CCU->pll_periph_ctrl)))
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return RT_ERROR;
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temp_data = CCU->ahb_apb_hclkc_cfg;
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temp_data &= ~(0x3 << 12);
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temp_data |= (clk_src << 12);
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CCU->ahb_apb_hclkc_cfg = temp_data;
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return RT_EOK;
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}
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rt_err_t cpu_set_clk(int clk)
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{
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if (clk < _24MHZ_)
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return RT_EINVAL;
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if (clk == cpu_get_clk())
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return RT_EOK;
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CCU->cpu_clk_src = CLK_OSC24M_SRC << 16;
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if (clk == _24MHZ_)
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return RT_EOK;
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if (cpu_set_pll_clk(clk))
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return RT_ERROR;
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CCU->ahb_apb_hclkc_cfg &= ~(0x3 << 16);
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CCU->cpu_clk_src = CLK_PLL_SRC << 16;
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return RT_EOK;
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}
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rt_err_t bus_gate_clk_enalbe(enum bus_gate bus)
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{
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rt_uint32_t offset;
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rt_uint32_t gate_reg;
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offset = bus & 0xfff;
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gate_reg = bus >> BUS_GATE_OFFSET_BIT;
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if (gate_reg == 0x00)
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CCU->bus_clk_gating0 |= (0x1 << offset);
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else if (gate_reg == 0x01)
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CCU->bus_clk_gating1 |= (0x1 << offset);
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else if (gate_reg == 0x02)
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CCU->bus_clk_gating2 |= (0x1 << offset);
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else
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return RT_EINVAL;
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return RT_EOK;
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}
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rt_err_t bus_gate_clk_disalbe(enum bus_gate bus)
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{
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rt_uint32_t offset;
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rt_uint32_t gate_reg;
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offset = bus & 0xfff;
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gate_reg = bus >> BUS_GATE_OFFSET_BIT;
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if (gate_reg == 0x00)
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CCU->bus_clk_gating0 &= ~(0x1 << offset);
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else if (gate_reg == 0x01)
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CCU->bus_clk_gating1 &= ~(0x1 << offset);
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else if (gate_reg == 0x02)
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CCU->bus_clk_gating2 &= ~(0x1 << offset);
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else
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return RT_EINVAL;
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return RT_EOK;
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}
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rt_err_t bus_software_reset_disalbe(enum bus_gate bus)
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{
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rt_uint32_t offset;
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rt_uint32_t gate_reg;
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offset = bus & 0xfff;
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gate_reg = bus >> BUS_GATE_OFFSET_BIT;
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if (gate_reg == 0x00)
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CCU->bus_soft_rst0 |= (0x1 << offset);
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else if (gate_reg == 0x01)
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CCU->bus_soft_rst1 |= (0x1 << offset);
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else if (gate_reg == 0x02)
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CCU->bus_soft_rst2 |= (0x1 << offset);
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else
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return RT_EINVAL;
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return RT_EOK;
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}
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rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
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{
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rt_uint32_t offset;
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rt_uint32_t gate_reg;
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offset = bus & 0xfff;
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gate_reg = bus >> BUS_GATE_OFFSET_BIT;
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if (gate_reg == 0x00)
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CCU->bus_soft_rst0 &= ~(0x1 << offset);
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else if (gate_reg == 0x01)
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CCU->bus_soft_rst1 &= ~(0x1 << offset);
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else if (gate_reg == 0x02)
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CCU->bus_soft_rst2 &= ~(0x1 << offset);
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else
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return RT_EINVAL;
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return RT_EOK;
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}
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rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
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{
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unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
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volatile rt_uint32_t *mmc_clk = (clk_id == SDMMC0) ? \
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(&CCU->sdmmc0_clk) : (&CCU->sdmmc1_clk);
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if (hz < 0)
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{
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return RT_EINVAL;
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}
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if (hz == 0)
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{
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*mmc_clk &= ~(0x1 << 31);
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return RT_EOK;
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}
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if (hz <= 24000000)
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{
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pll = (0x0 << 24);
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pll_hz = 24000000;
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}
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else
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{
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pll = (0x1 << 24);
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pll_hz = periph_get_pll_clk();
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}
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div = pll_hz / hz;
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if (pll_hz % hz)
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{
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div++;
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}
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n = 0;
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while (div > 16)
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{
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n++;
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div = (div + 1) / 2;
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}
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if (n > 3)
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{
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return -1;
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}
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/* determine delays */
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if (hz <= 400000)
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{
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oclk_dly = 0;
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sclk_dly = 0;
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}
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else if (hz <= 25000000)
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{
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oclk_dly = 0;
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sclk_dly = 5;
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}
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else if (hz <= 50000000)
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{
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oclk_dly = 3;
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sclk_dly = 4;
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}
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else
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{
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/* hz > 50000000 */
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oclk_dly = 1;
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sclk_dly = 4;
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}
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*mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
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(n << 16) | (oclk_dly << 8) | (div - 1);
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return RT_EOK;
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}
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rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate)
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{
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CCU->dram_gating |= (0x01 << dram_gate);
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return RT_EOK;
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}
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|
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rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate)
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{
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CCU->dram_gating &= ~(0x01 << dram_gate);
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return RT_EOK;
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}
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