263 lines
9.7 KiB
C
263 lines
9.7 KiB
C
/*
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* drv_dmic.h
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*
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* Created on: 2017Äê1ÔÂ11ÈÕ
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* Author: Urey
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*/
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#ifndef _DRV_DMIC_H_
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#define _DRV_DMIC_H_
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/*
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* File : drv_dmic.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-11-19 Urey the first version
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*/
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#include <dma.h>
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#include "audio_pipe.h"
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#define DMIC_DMA_PAGE_SIZE 512
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#define DMIC_DMA_PAGE_NUM RT_DMA_MAX_NODES
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struct jz_dmic
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{
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struct rt_audio_pipe pipe;
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struct rt_audio_configure record_config;
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uint32_t io_base;
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struct clk *clk_gate;
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struct rt_dma_channel *rx_dmac;
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rt_uint8_t *dma_buf;
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rt_uint32_t dma_offset;
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/* record */
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int record_gain;
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};
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static inline void dmic_write_reg(struct jz_dmic *dmic, uint32_t reg, uint32_t val)
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{
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writel(val, dmic->io_base + reg);
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}
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static inline uint32_t dmic_read_reg(struct jz_dmic *jz_dmic, unsigned int reg)
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{
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return readl(jz_dmic->io_base + reg);
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}
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#define dmic_set_reg(dmic, addr, val, mask, offset)\
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do { \
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int tmp_val = val; \
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int read_val = dmic_read_reg(dmic, addr); \
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read_val &= (~mask); \
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tmp_val = ((tmp_val << offset) & mask); \
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tmp_val |= read_val; \
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dmic_write_reg(dmic, addr, tmp_val); \
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}while(0)
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#define dmic_get_reg(dmic, addr, mask, offset) \
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((dmic_read_reg(dmic, addr) & mask) >> offset)
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/*********************************************************************************************************
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**
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*********************************************************************************************************/
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#define DMICCR0 0x00
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#define DMICGCR 0x04
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#define DMICIMR 0x08
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#define DMICINTCR 0x0c
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#define DMICTRICR 0x10
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#define DMICTHRH 0x14
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#define DMICTHRL 0x18
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#define DMICTRIMMAX 0x1c
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#define DMICTRINMAX 0x20
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#define DMICDR 0x30
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#define DMICFTHR 0x34
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#define DMICFSR 0x38
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#define DMICCGDIS 0x50
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/* DMICCR0 */
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#define DMIC_RESET 31
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#define DMIC_RESET_MASK (0x1 << DMIC_RESET)
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#define DMIC_RESET_TRI 30
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#define DMIC_RESET_TRI_MASK (0x1 << DMIC_RESET_TRI)
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#define DMIC_CHNUM 16
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#define DMIC_CHNUM_MASK (0x7 << DMIC_CHNUM)
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#define DMIC_UNPACK_MSB 13
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#define DMIC_UNPACK_MSB_MASK (0x1 << DMIC_UNPACK_MSB)
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#define DMIC_UNPACK_DIS 12
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#define DMIC_UNPACK_DIS_MASK (0x1 << DMIC_UNPACK_DIS)
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#define DMIC_SW_LR 11
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#define DMIC_SW_LR_MASK (0x1 << DMIC_SW_LR)
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#define DMIC_SPLIT_DI 10
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#define DMIC_SPLIT_DI_MASK (0x1 << DMIC_SPLIT_DI)
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#define DMIC_PACK_EN 8
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#define DMIC_PACK_EN_MASK (0x1 << DMIC_PACK_EN)
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#define DMIC_SR 6
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#define DMIC_SR_MASK (0x3 << DMIC_SR)
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#define DMIC_LP_MODE 3
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#define DMIC_LP_MODE_MASK (0x1 << DMIC_LP_MODE)
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#define DMIC_HPF1_MODE 2
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#define DMIC_HPF1_MODE_MASK (0x1 << DMIC_HPF1_MODE)
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#define DMIC_TRI_EN 1
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#define DMIC_TRI_EN_MASK (0x1 << DMIC_TRI_EN)
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#define DMIC_EN 0
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#define DMIC_EN_MASK (0x1 << DMIC_EN)
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#define __dmic_reset(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_RESET_MASK,DMIC_RESET)
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#define __dmic_get_reset(dmic)\
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dmic_get_reg(dmic,DMICCR0,DMIC_RESET_MASK,DMIC_RESET)
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#define __dmic_reset_tri(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_RESET_TRI_MASK,DMIC_RESET_TRI)
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#define __dmic_set_chnum(dmic,n)\
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dmic_set_reg(dmic,DMICCR0,n,DMIC_CHNUM_MASK,DMIC_CHNUM)
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#define __dmic_get_chnum(dmic,n)\
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dmic_set_reg(dmic,DMICCR0,DMIC_CHNUM_MASK,DMIC_CHNUM)
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#define __dmic_unpack_msb(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_UNPACK_MSB_MASK,DMIC_UNPACK_MSB)
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#define __dmic_unpack_dis(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_UNPACK_DIS_MASK,DMIC_UNPACK_DIS)
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#define __dmic_enable_sw_lr(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_SW_LR_MASK,DMIC_SW_LR)
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#define __dmic_disable_sw_lr(dmic)\
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dmic_set_reg(dmic,DMICCR0,0,DMIC_SW_LR_MASK,DMIC_SW_LR)
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#define __dmic_split(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_SPLIT_DI_MASK,DMIC_SPLIT_DI)
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#define __dmic_enable_pack(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_PACK_EN_MASK,DMIC_PACK_EN)
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#define __dmic_set_sr(dmic,n)\
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dmic_set_reg(dmic,DMICCR0,n,DMIC_SR_MASK,DMIC_SR)
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#define __dmic_set_sr_8k(dmic)\
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__dmic_set_sr(dmic,0)
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#define __dmic_set_sr_16k(dmic)\
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__dmic_set_sr(dmic,1)
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#define __dmic_set_sr_48k(dmic)\
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__dmic_set_sr(dmic,2)
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#define __dmic_enable_lp(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_LP_MODE_MASK,DMIC_LP_MODE)
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#define __dmic_disable_lp(dmic)\
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dmic_set_reg(dmic,DMICCR0,0,DMIC_LP_MODE_MASK,DMIC_LP_MODE)
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#define __dmic_enable_hpf1(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_HPF1_MODE_MASK,DMIC_HPF1_MODE)
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#define __dmic_disable_hpf1(dmic)\
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dmic_set_reg(dmic,DMICCR0,0,DMIC_HPF1_MODE_MASK,DMIC_HPF1_MODE)
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#define __dmic_is_enable_tri(dmic)\
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dmic_get_reg(dmic,DMICCR0,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
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#define __dmic_enable_tri(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
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#define __dmic_disable_tri(dmic)\
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dmic_set_reg(dmic,DMICCR0,0,DMIC_TRI_EN_MASK,DMIC_TRI_EN)
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#define __dmic_is_enable(dmic)\
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dmic_get_reg(dmic,DMICCR0,DMIC_EN_MASK,DMIC_EN)
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#define __dmic_enable(dmic)\
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dmic_set_reg(dmic,DMICCR0,1,DMIC_EN_MASK,DMIC_EN)
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#define __dmic_disable(dmic)\
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dmic_set_reg(dmic,DMICCR0,0,DMIC_EN_MASK,DMIC_EN)
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/*DMICGCR*/
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#define DMIC_GCR 0
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#define DMIC_GCR_MASK (0Xf << DMIC_GCR)
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#define __dmic_set_gcr(dmic,n)\
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dmic_set_reg(dmic, DMICGCR, n, DMIC_GCR_MASK,DMIC_GCR)
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/* DMICIMR */
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#define DMIC_FIFO_TRIG_MASK 5
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#define DMIC_FIFO_TRIG_MSK (1 << DMIC_FIFO_TRIG_MASK)
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#define DMIC_WAKE_MASK 4
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#define DMIC_WAKE_MSK (1 << DMIC_WAKE_MASK)
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#define DMIC_EMPTY_MASK 3
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#define DMIC_EMPTY_MSK (1 << DMIC_EMPTY_MASK)
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#define DMIC_FULL_MASK 2
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#define DMIC_FULL_MSK (1 << DMIC_FULL_MASK)
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#define DMIC_PRERD_MASK 1
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#define DMIC_PRERD_MSK (1 << DMIC_PRERD_MASK)
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#define DMIC_TRI_MASK 0
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#define DMIC_TRI_MSK (1 << DMIC_TRI_MASK)
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#define __dmic_mask_all_int(dmic)\
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dmic_set_reg(dmic,DMICIMR, 0x3f, 0x3f, 0)
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/*DMICINTCR*/
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#define DMIC_FIFO_TRIG_FLAG 4
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#define DMIC_FIFO_TRIG_FLAG_MASK (1 << DMIC_WAKE_FLAG)
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#define DMIC_WAKE_FLAG 4
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#define DMIC_WAKE_FLAG_MASK (1 << DMIC_WAKE_FLAG)
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#define DMIC_EMPTY_FLAG 3
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#define DMIC_EMPTY_FLAG_MASK (1 << DMIC_EMPTY_FLAG)
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#define DMIC_FULL_FLAG 2
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#define DMIC_FULL_FLAG_MASK (1 << DMIC_FULL_FLAG)
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#define DMIC_PRERD_FLAG 1
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#define DMIC_PRERD_FLAG_MASK (1 << DMIC_PRERD_FLAG)
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#define DMIC_TRI_FLAG 0
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#define DMIC_TRI_FLAG_MASK (1 << DMIC_TRI_FLAG)
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/*DMICTRICR*/
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#define DMIC_TRI_MODE 16
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#define DMIC_TRI_MODE_MASK (0xf << DMIC_TRI_MODE)
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#define DMIC_TRI_DEBUG 4
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#define DMIC_TRI_DEBUG_MASK (0x1 << DMIC_TRI_DEBUG)
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#define DMIC_HPF2_EN 3
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#define DMIC_HPF2_EN_MASK (0x1 << DMIC_HPF2_EN)
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#define DMIC_PREFETCH 1
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#define DMIC_PREFETCH_MASK (0x3 << DMIC_PREFETCH)
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#define DMIC_TRI_CLR 0
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#define DMIC_TRI_CLR_MASK (0x1 << DMIC_TRI_CLR)
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#define __dmic_enable_hpf2(dmic) \
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dmic_set_reg(dmic, DMICTRICR, 1, DMIC_HPF2_EN_MASK, DMIC_HPF2_EN)
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#define __dmic_disable_hpf2(dmic) \
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dmic_set_reg(dmic, DMICTRICR, 0, DMIC_HPF2_EN_MASK, DMIC_HPF2_EN)
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/*DMICTHRH*/
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#define DMIC_THR_H 0
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#define DMIC_THR_H_MASK (0xfffff << DMIC_THR_H)
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#define __dmic_set_thr_high(dmic,n) \
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dmic_set_reg(dmic, DMICTHRH, n, DMIC_THR_H_MASK, DMIC_THR_H)
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/*DMICTHRL*/
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#define DMIC_THR_L 0
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#define DMIC_THR_L_MASK (0xfffff << DMIC_THR_L)
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#define __dmic_set_thr_low(dmic,n) \
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dmic_set_reg(dmic, DMICTHRL, n, DMIC_THR_L_MASK, DMIC_THR_L)
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/* DMICTRIMMAX */
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#define DMIC_M_MAX 0
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#define DMIC_M_MAX_MASK (0xffffff << DMIC_M_MAX)
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/* DMICTRINMAX */
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#define DMIC_N_MAX 0
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#define DMIC_N_MAX_MASK (0xffff << DMIC_N_MAX)
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/* DMICFTHR */
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#define DMIC_RDMS 31
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#define DMIC_RDMS_MASK (0x1 << DMIC_RDMS)
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#define DMIC_FIFO_THR 0
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#define DMIC_FIFO_THR_MASK (0x3f << DMIC_FIFO_THR)
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#define __dmic_is_enable_rdms(dmic)\
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dmic_get_reg(dmic, DMICFTHR,DMIC_RDMS_MASK,DMIC_RDMS)
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#define __dmic_enable_rdms(dmic)\
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dmic_set_reg(dmic, DMICFTHR,1,DMIC_RDMS_MASK,DMIC_RDMS)
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#define __dmic_disable_rdms(dmic)\
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dmic_set_reg(dmic, DMICFTHR,1,DMIC_RDMS_MASK,DMIC_RDMS)
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#define __dmic_set_request(dmic,n) \
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dmic_set_reg(dmic, DMICFTHR, n, DMIC_FIFO_THR_MASK, DMIC_FIFO_THR)
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/*DMICFSR*/
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#define DMIC_FULLS 19
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#define DMIC_FULLS_MASK (0x1 << DMIC_FULLS)
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#define DMIC_TRIGS 18
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#define DMIC_TRIGS_MASK (0x1 << DMIC_TRIGS)
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#define DMIC_PRERDS 17
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#define DMIC_PRERDS_MASK (0x1 << DMIC_PRERDS)
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#define DMIC_EMPTYS 16
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#define DMIC_EMPTYS_MASK (0x1 << DMIC_EMPTYS)
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#define DMIC_FIFO_LVL 0
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#define DMIC_FIFO_LVL_MASK (0x3f << DMIC_FIFO_LVL)
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/*********************************************************************************************************
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**
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*********************************************************************************************************/
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struct jz_dmic* rt_hw_dmic_init(void);
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int jz_dmic_set_rate(struct jz_dmic* dmic, int rate);
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int jz_dmic_set_gain(struct jz_dmic* dmic, int vol);
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int jz_dmic_set_channels(struct jz_dmic* dmic, int channels);
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#endif /* _DRV_DMIC_H_ */
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