144 lines
3.9 KiB
C
144 lines
3.9 KiB
C
/*
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* COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "zynq7000.h"
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#include "cp15.h"
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#include "gic.h"
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#define MAX_HANDLERS IRQ_Zynq7000_MAXNR
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extern volatile rt_uint8_t rt_interrupt_nest;
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/* exception and interrupt handler table */
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struct rt_irq_desc isr_table[MAX_HANDLERS];
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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static void rt_hw_interrupt_handle(int vector, void *param)
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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}
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const unsigned int VECTOR_BASE = 0x00;
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extern int system_vectors;
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static void rt_hw_vector_init(void)
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{
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int sctrl;
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unsigned int *src = (unsigned int *)&system_vectors;
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/* C12-C0 is only active when SCTLR.V = 0 */
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asm volatile ("mrc p15, #0, %0, c1, c0, #0"
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:"=r" (sctrl));
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sctrl &= ~(1 << 13);
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asm volatile ("mcr p15, #0, %0, c1, c0, #0"
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:
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:"r" (sctrl));
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asm volatile ("mcr p15, #0, %0, c12, c0, #0"
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:
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:"r" (src));
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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register rt_uint32_t idx;
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/* set vector table */
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rt_hw_vector_init();
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/* init exceptions table */
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rt_memset(isr_table, 0x00, sizeof(isr_table));
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for (idx = 0; idx < MAX_HANDLERS; idx++)
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{
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isr_table[idx].handler = rt_hw_interrupt_handle;
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}
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/* initialize ARM GIC */
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arm_gic_dist_init(0, Zynq7000_GIC_DIST_BASE, 0);
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arm_gic_cpu_init(0, Zynq7000_GIC_CPU_BASE);
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int vector)
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{
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arm_gic_mask(0, vector);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int vector)
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{
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arm_gic_umask(0, vector);
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void *param, char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector < MAX_HANDLERS)
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{
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old_handler = isr_table[vector].handler;
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if (handler != RT_NULL)
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{
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#ifdef RT_USING_INTERRUPT_INFO
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rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
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#endif /* RT_USING_INTERRUPT_INFO */
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isr_table[vector].handler = handler;
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isr_table[vector].param = param;
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}
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/* set the interrupt to this cpu */
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arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
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}
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return old_handler;
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}
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void rt_hw_interrupt_clear(int vector)
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{
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/* SGI will be cleared automatically. */
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if (vector < 16)
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return;
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}
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