611 lines
27 KiB
C
611 lines
27 KiB
C
/*
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* File : drv_emac.c
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* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-08-08 Yang the first version
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*/
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#include <rtthread.h>
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#include "lwipopts.h"
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#include <netif/ethernetif.h>
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#include <board.h>
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#include "drv_emac.h"
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#include "fsl_iocon.h"
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#include "fsl_sctimer.h"
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#include "fsl_phy.h"
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#define IOCON_PIO_DIGITAL_EN 0x0100u /*!< Enables digital function */
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#define IOCON_PIO_FUNC0 0x00u /*!< Selects pin function 0 */
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#define IOCON_PIO_FUNC1 0x01u /*!< Selects pin function 1 */
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#define IOCON_PIO_FUNC7 0x07u /*!< Selects pin function 7 */
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#define IOCON_PIO_INPFILT_OFF 0x0200u /*!< Input filter disabled */
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#define IOCON_PIO_INV_DI 0x00u /*!< Input function is not inverted */
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#define IOCON_PIO_MODE_INACT 0x00u /*!< No addition pin function */
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#define IOCON_PIO_MODE_PULLUP 0x20u /*!< Selects pull-up function */
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#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!< Open drain is disabled */
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#define IOCON_PIO_SLEW_FAST 0x0400u /*!< Fast mode, slew rate control is disabled */
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#define IOCON_PIO_SLEW_STANDARD 0x00u /*!< Standard mode, output slew rate control is enabled */
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#define PIN8_IDX 8u /*!< Pin number for pin 8 in a port 4 */
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#define PIN10_IDX 10u /*!< Pin number for pin 10 in a port 4 */
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#define PIN11_IDX 11u /*!< Pin number for pin 11 in a port 4 */
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#define PIN12_IDX 12u /*!< Pin number for pin 12 in a port 4 */
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#define PIN13_IDX 13u /*!< Pin number for pin 13 in a port 4 */
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#define PIN14_IDX 14u /*!< Pin number for pin 14 in a port 4 */
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#define PIN15_IDX 15u /*!< Pin number for pin 15 in a port 4 */
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#define PIN16_IDX 16u /*!< Pin number for pin 16 in a port 4 */
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#define PIN17_IDX 17u /*!< Pin number for pin 17 in a port 0 */
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#define PIN26_IDX 26u /*!< Pin number for pin 26 in a port 2 */
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#define PIN29_IDX 29u /*!< Pin number for pin 29 in a port 0 */
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#define PIN30_IDX 30u /*!< Pin number for pin 30 in a port 0 */
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#define PORT0_IDX 0u /*!< Port index */
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#define PORT2_IDX 2u /*!< Port index */
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#define PORT4_IDX 4u /*!< Port index */
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#define EMAC_PHY_AUTO 0
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#define EMAC_PHY_10MBIT 1
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#define EMAC_PHY_100MBIT 2
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#define MAX_ADDR_LEN 6
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/* EMAC_RAM_BASE is defined in board.h and the size is 16KB */
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#define RX_DESC_BASE ETH_RAM_BASE
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#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
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#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
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#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
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#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
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#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
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/* RX and TX descriptor and status definitions. */
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#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
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#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
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#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
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#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
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#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
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#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
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#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
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#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
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#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
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struct lpc_emac
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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rt_uint8_t phy_mode;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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static struct lpc_emac lpc_emac_device;
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static struct rt_semaphore sem_lock;
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static struct rt_event tx_event;
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#if defined(__GNUC__)
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#ifndef __ALIGN_END
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#define __ALIGN_END __attribute__((aligned(ENET_BUFF_ALIGNMENT)))
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#endif
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#ifndef __ALIGN_BEGIN
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#define __ALIGN_BEGIN
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#endif
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#else
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#ifndef __ALIGN_END
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#define __ALIGN_END
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#endif
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#ifndef __ALIGN_BEGIN
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#if defined(__CC_ARM)
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#define __ALIGN_BEGIN __align(ENET_BUFF_ALIGNMENT)
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#elif defined(__ICCARM__)
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#define __ALIGN_BEGIN
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#endif
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#endif
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#endif
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#define ENET_RXBD_NUM (4)
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#define ENET_TXBD_NUM (4)
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#define PHY_ADDR (0x00U)
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#define ENET_LOOP_COUNT (20U)
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#define ENET_ALIGN(x, align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)-1)))
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#define ENET_BuffSizeAlign(n) ENET_ALIGN(n, ENET_BUFF_ALIGNMENT)
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__ALIGN_BEGIN enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] __ALIGN_END;
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__ALIGN_BEGIN enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] __ALIGN_END;
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uint8_t multicastAddr[6] = {0x01, 0x00, 0x5e, 0x00, 0x01, 0x81};
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uint8_t *g_txbuff[ENET_TXBD_NUM];
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uint32_t g_txIdx = 0;
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uint8_t g_txbuffIdx = 0;
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uint8_t g_txGenIdx = 0;
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uint8_t g_txCosumIdx = 0;
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uint8_t g_txUsed = 0;
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uint8_t g_rxGenIdx = 0;
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uint32_t g_rxCosumIdx = 0;
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uint32_t g_rxbuffer[ENET_RXBD_NUM];
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static uint8_t *ENET_RXRead(int32_t *length)
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{
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uint32_t control;
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uint8_t *data;
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*length = 0;
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/* Get the Frame size */
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control = ENET_GetRxDescriptor(&g_rxBuffDescrip[g_rxGenIdx]);
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if (!(control & ENET_RXDESCRIP_RD_OWN_MASK))
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{
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if (control & ENET_RXDESCRIP_WR_LD_MASK)
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{
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/* if no error */
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if (control & ENET_RXDESCRIP_WR_ERRSUM_MASK)
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{
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*length = -1;
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}
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else
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{
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*length = control & ENET_RXDESCRIP_WR_PACKETLEN_MASK;
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data = (uint8_t *)g_rxbuffer[g_rxGenIdx];
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}
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g_rxGenIdx = (g_rxGenIdx + 1) % ENET_RXBD_NUM;
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}
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}
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return data;
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}
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static void ENET_RXClaim(uint8_t* buffer)
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{
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if (ENET_GetDmaInterruptStatus(ENET, 0) & kENET_DmaRxBuffUnavail)
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{
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ENET_UpdateRxDescriptor(&g_rxBuffDescrip[g_rxCosumIdx], buffer, NULL, true, false);
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/* Command for rx poll when the dma suspend. */
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ENET_UpdateRxDescriptorTail(ENET, 0, (uint32_t)&g_rxBuffDescrip[ENET_RXBD_NUM]);
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}
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else
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{
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ENET_UpdateRxDescriptor(&g_rxBuffDescrip[g_rxCosumIdx], buffer, NULL, true, false);
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}
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if (buffer)
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{
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g_rxbuffer[g_rxCosumIdx] = (uint32_t)buffer;
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}
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g_rxCosumIdx = (g_rxCosumIdx + 1) % ENET_RXBD_NUM;
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}
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static status_t ENET_TXQueue(uint8_t *data, uint16_t length)
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{
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uint32_t txdescTailAddr;
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/* Fill the descriptor. */
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if (ENET_IsTxDescriptorDmaOwn(&g_txBuffDescrip[g_txGenIdx]))
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{
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return kStatus_Fail;
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}
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ENET_SetupTxDescriptor(&g_txBuffDescrip[g_txGenIdx], data, length, NULL, 0, length, true, false, kENET_FirstLastFlag, 0);
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/* Increase the index. */
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g_txGenIdx = (g_txGenIdx + 1) % ENET_TXBD_NUM;
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g_txUsed++;
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/* Update the transmit tail address. */
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txdescTailAddr = (uint32_t)&g_txBuffDescrip[g_txGenIdx];
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if (!g_txGenIdx)
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{
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txdescTailAddr = (uint32_t)&g_txBuffDescrip[ENET_TXBD_NUM];
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}
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ENET_UpdateTxDescriptorTail(ENET, 0, txdescTailAddr);
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return kStatus_Success;
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}
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static void ENET_TXReclaim()
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{
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if (!ENET_IsTxDescriptorDmaOwn(&g_txBuffDescrip[g_txCosumIdx]) && (g_txUsed > 0))
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{
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/* Free tx buffers. */
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free(g_txbuff[g_txCosumIdx]);
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g_txUsed--;
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g_txCosumIdx = (g_txCosumIdx + 1) % ENET_TXBD_NUM;
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}
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}
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void ETHERNET_IRQHandler(void)
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{
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/* Check for the interrupt source type. */
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/* DMA CHANNEL 0. */
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uint32_t status;
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/* enter interrupt */
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rt_interrupt_enter();
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status = ENET_GetDmaInterruptStatus(ENET, 0);
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if (status)
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{
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if (status & kENET_DmaRx)
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{
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/* a frame has been received */
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eth_device_ready(&(lpc_emac_device.parent));
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}
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if (status & kENET_DmaTx)
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{
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/* set event */
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rt_event_send(&tx_event, 0x01);
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}
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/* Clear the interrupt. */
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ENET_ClearDmaInterruptStatus(ENET, 0, status);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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static rt_err_t lpc_emac_init(rt_device_t dev)
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{
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int32_t status, index;
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void *buff;
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phy_speed_t speed;
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phy_duplex_t duplex;
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enet_config_t config;
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bool link = false;
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uint32_t timedelay;
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uint32_t refClock = 50000000; /* 50MHZ for rmii reference clock. */
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for (index = 0; index < ENET_RXBD_NUM; index++)
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{
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/* This is for rx buffers, static alloc and dynamic alloc both ok. use as your wish. */
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buff = rt_malloc(ENET_FRAME_MAX_FRAMELEN);
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if (buff)
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{
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g_rxbuffer[index] = (uint32_t)buff;
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}
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else
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{
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rt_kprintf("Mem Alloc fail\r\n");
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}
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}
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/* prepare the buffer configuration. */
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enet_buffer_config_t buffConfig =
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{
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ENET_RXBD_NUM,
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ENET_TXBD_NUM,
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&g_txBuffDescrip[0],
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&g_txBuffDescrip[0],
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&g_rxBuffDescrip[0],
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&g_rxBuffDescrip[4],
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&g_rxbuffer[0],
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ENET_BuffSizeAlign(ENET_FRAME_MAX_FRAMELEN),
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};
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{
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const uint32_t port0_pin17_config = (
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IOCON_PIO_FUNC7 | /* Pin is configured as ENET_TXD1 */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN17_IDX, port0_pin17_config); /* PORT0 PIN17 (coords: E14) is configured as ENET_TXD1 */
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const uint32_t port2_pin26_config = (
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IOCON_PIO_FUNC0 | /* Pin is configured as PIO2_26 */
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IOCON_PIO_MODE_PULLUP | /* Selects pull-up function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT2_IDX, PIN26_IDX, port2_pin26_config); /* PORT2 PIN26 (coords: H11) is configured as PIO2_26 */
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const uint32_t port4_pin10_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_RX_DV */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN10_IDX, port4_pin10_config); /* PORT4 PIN10 (coords: B9) is configured as ENET_RX_DV */
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const uint32_t port4_pin11_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_RXD0 */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN11_IDX, port4_pin11_config); /* PORT4 PIN11 (coords: A9) is configured as ENET_RXD0 */
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const uint32_t port4_pin12_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_RXD1 */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN12_IDX, port4_pin12_config); /* PORT4 PIN12 (coords: A6) is configured as ENET_RXD1 */
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const uint32_t port4_pin13_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_TX_EN */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN13_IDX, port4_pin13_config); /* PORT4 PIN13 (coords: B6) is configured as ENET_TX_EN */
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const uint32_t port4_pin14_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_RX_CLK */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN14_IDX, port4_pin14_config); /* PORT4 PIN14 (coords: B5) is configured as ENET_RX_CLK */
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const uint32_t port4_pin15_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_MDC */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN15_IDX, port4_pin15_config); /* PORT4 PIN15 (coords: A4) is configured as ENET_MDC */
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const uint32_t port4_pin16_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_MDIO */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
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IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
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);
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IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN16_IDX, port4_pin16_config); /* PORT4 PIN16 (coords: C4) is configured as ENET_MDIO */
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const uint32_t port4_pin8_config = (
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IOCON_PIO_FUNC1 | /* Pin is configured as ENET_TXD0 */
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IOCON_PIO_MODE_INACT | /* No addition pin function */
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IOCON_PIO_INV_DI | /* Input function is not inverted */
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IOCON_PIO_DIGITAL_EN | /* Enables digital function */
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IOCON_PIO_INPFILT_OFF | /* Input filter disabled */
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IOCON_PIO_SLEW_STANDARD | /* Standard mode, output slew rate control is enabled */
|
|
IOCON_PIO_OPENDRAIN_DI /* Open drain is disabled */
|
|
);
|
|
IOCON_PinMuxSet(IOCON, PORT4_IDX, PIN8_IDX, port4_pin8_config); /* PORT4 PIN8 (coords: B14) is configured as ENET_TXD0 */
|
|
}
|
|
|
|
status = PHY_Init(ENET, PHY_ADDR, 0);
|
|
if (status == kStatus_Success)
|
|
{
|
|
PHY_GetLinkSpeedDuplex(ENET, PHY_ADDR, &speed, &duplex);
|
|
/* Use the actual speed and duplex when phy success to finish the autonegotiation. */
|
|
config.miiSpeed = (enet_mii_speed_t)speed;
|
|
config.miiDuplex = (enet_mii_duplex_t)duplex;
|
|
}
|
|
else
|
|
{
|
|
rt_kprintf("PHY_Init failed!\n");
|
|
return RT_ERROR;
|
|
}
|
|
|
|
/* Wait for link up and get the actual PHY link speed. */
|
|
PHY_GetLinkStatus(ENET, PHY_ADDR, &link);
|
|
while (!link)
|
|
{
|
|
rt_kprintf("PHY Wait for link up!\n");
|
|
for (timedelay = 0; timedelay < 0xFFFFFU; timedelay++)
|
|
{
|
|
__ASM("nop");
|
|
}
|
|
PHY_GetLinkStatus(ENET, PHY_ADDR, &link);
|
|
}
|
|
|
|
/* Get default configuration 100M RMII. */
|
|
ENET_GetDefaultConfig(&config);
|
|
|
|
/* Initialize ENET. */
|
|
ENET_Init(ENET, &config, &lpc_emac_device.dev_addr[0], refClock);
|
|
|
|
/* Enable the tx/rx interrupt. */
|
|
ENET_EnableInterrupts(ENET, (kENET_DmaTx | kENET_DmaRx));
|
|
EnableIRQ(ETHERNET_IRQn);
|
|
|
|
/* Initialize Descriptor. */
|
|
ENET_DescriptorInit(ENET, &config, &buffConfig);
|
|
|
|
/* Active TX/RX. */
|
|
ENET_StartRxTx(ENET, 1, 1);
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
static rt_err_t lpc_emac_open(rt_device_t dev, rt_uint16_t oflag)
|
|
{
|
|
return RT_EOK;
|
|
}
|
|
|
|
static rt_err_t lpc_emac_close(rt_device_t dev)
|
|
{
|
|
return RT_EOK;
|
|
}
|
|
|
|
static rt_size_t lpc_emac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
|
{
|
|
rt_set_errno(-RT_ENOSYS);
|
|
return 0;
|
|
}
|
|
|
|
static rt_size_t lpc_emac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
|
{
|
|
rt_set_errno(-RT_ENOSYS);
|
|
return 0;
|
|
}
|
|
|
|
static rt_err_t lpc_emac_control(rt_device_t dev, int cmd, void *args)
|
|
{
|
|
switch (cmd)
|
|
{
|
|
case NIOCTL_GADDR:
|
|
/* get mac address */
|
|
if (args) rt_memcpy(args, lpc_emac_device.dev_addr, 6);
|
|
else return -RT_ERROR;
|
|
break;
|
|
|
|
default :
|
|
break;
|
|
}
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
/* EtherNet Device Interface */
|
|
/* transmit packet. */
|
|
rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p)
|
|
{
|
|
rt_uint8_t *buffer;
|
|
rt_err_t result;
|
|
rt_uint32_t recved;
|
|
|
|
/* lock EMAC device */
|
|
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
|
|
|
/* there is no block yet, wait a flag */
|
|
result = rt_event_recv(&tx_event, 0x01, RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_NO, &recved);
|
|
if (result == RT_EOK)
|
|
ENET_TXReclaim();
|
|
|
|
/* Create the buffer for zero-copy transmit. */
|
|
buffer = (uint8_t *)malloc(p->tot_len);
|
|
if (buffer)
|
|
{
|
|
/* copy data to tx buffer */
|
|
pbuf_copy_partial(p, buffer, p->tot_len, 0);
|
|
|
|
while ((g_txbuffIdx + 1) % ENET_TXBD_NUM == g_txCosumIdx)
|
|
{
|
|
rt_thread_delay(RT_TICK_PER_SECOND / 20); // 50 ms
|
|
}
|
|
|
|
/* Store the buffer for mem free. */
|
|
g_txbuff[g_txbuffIdx] = buffer;
|
|
g_txbuffIdx = (g_txbuffIdx + 1) % ENET_TXBD_NUM;
|
|
/* Send the frame out (wait unitl the descriptor ready). */
|
|
while (ENET_TXQueue(buffer, p->tot_len) != kStatus_Success);
|
|
}
|
|
|
|
/* unlock EMAC device */
|
|
rt_sem_release(&sem_lock);
|
|
|
|
return RT_EOK;
|
|
}
|
|
|
|
/* reception packet. */
|
|
struct pbuf *lpc_emac_rx(rt_device_t dev)
|
|
{
|
|
struct pbuf *p;
|
|
uint8_t *data;
|
|
int length;
|
|
|
|
/* init p pointer */
|
|
p = RT_NULL;
|
|
|
|
/* lock EMAC device */
|
|
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
|
|
|
length = 0;
|
|
data = ENET_RXRead(&length);
|
|
if (length > 0)
|
|
{
|
|
void *buffer;
|
|
/* Update the buffers and then we can delivery the previous buffer diectly to
|
|
the application without memcpy. */
|
|
buffer = rt_malloc(ENET_FRAME_MAX_FRAMELEN);
|
|
if (buffer)
|
|
{
|
|
ENET_RXClaim(buffer);
|
|
}
|
|
else
|
|
{
|
|
ENET_RXClaim(NULL);
|
|
}
|
|
|
|
/* Do what you want to do with the data and then free the used one. */
|
|
p = pbuf_alloc(PBUF_LINK, length, PBUF_RAM);
|
|
if (p != RT_NULL)
|
|
{
|
|
rt_memcpy(p->payload, data, length);
|
|
p->tot_len = length;
|
|
}
|
|
rt_free(data);
|
|
}
|
|
else if (length < 0)
|
|
{
|
|
ENET_RXClaim(NULL);
|
|
}
|
|
|
|
/* unlock EMAC device */
|
|
rt_sem_release(&sem_lock);
|
|
|
|
return p;
|
|
}
|
|
|
|
int lpc_emac_hw_init(void)
|
|
{
|
|
rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
|
|
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
|
|
|
/* set autonegotiation mode */
|
|
lpc_emac_device.phy_mode = EMAC_PHY_AUTO;
|
|
|
|
// OUI 00-60-37 NXP Semiconductors
|
|
lpc_emac_device.dev_addr[0] = 0x00;
|
|
lpc_emac_device.dev_addr[1] = 0x60;
|
|
lpc_emac_device.dev_addr[2] = 0x37;
|
|
/* set mac address: (only for test) */
|
|
lpc_emac_device.dev_addr[3] = 0x12;
|
|
lpc_emac_device.dev_addr[4] = 0x34;
|
|
lpc_emac_device.dev_addr[5] = 0x56;
|
|
|
|
lpc_emac_device.parent.parent.init = lpc_emac_init;
|
|
lpc_emac_device.parent.parent.open = lpc_emac_open;
|
|
lpc_emac_device.parent.parent.close = lpc_emac_close;
|
|
lpc_emac_device.parent.parent.read = lpc_emac_read;
|
|
lpc_emac_device.parent.parent.write = lpc_emac_write;
|
|
lpc_emac_device.parent.parent.control = lpc_emac_control;
|
|
lpc_emac_device.parent.parent.user_data = RT_NULL;
|
|
|
|
lpc_emac_device.parent.eth_rx = lpc_emac_rx;
|
|
lpc_emac_device.parent.eth_tx = lpc_emac_tx;
|
|
|
|
eth_device_init(&(lpc_emac_device.parent), "e0");
|
|
return 0;
|
|
}
|
|
INIT_DEVICE_EXPORT(lpc_emac_hw_init);
|