395 lines
8.5 KiB
C
395 lines
8.5 KiB
C
/*
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* File : mmu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2008-04-25 Yi.qiu first version
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* 2009-12-18 Bernard port to armcc
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*/
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#include <rtthread.h>
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#include "s3c24x0.h"
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#define _MMUTT_STARTADDRESS 0x33FF0000
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#define DESC_SEC (0x2|(1<<4))
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define DOMAIN_FAULT (0x0)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
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#ifdef __GNUC__
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void mmu_setttbase(register rt_uint32_t i)
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{
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asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_invalidate_tlb()
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{
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asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidate_icache()
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{
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asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
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}
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#endif
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#ifdef __CC_ARM
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void mmu_setttbase(rt_uint32_t i)
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{
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__asm
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{
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mcr p15, 0, i, c2, c0, 0
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}
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}
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void mmu_set_domain(rt_uint32_t i)
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{
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__asm
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{
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mcr p15,0, i, c3, c0, 0
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}
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}
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void mmu_enable()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x01
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x1000
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x04
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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orr value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t value;
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__asm
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{
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mrc p15, 0, value, c1, c0, 0
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bic value, value, #0x02
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mcr p15, 0, value, c1, c0, 0
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}
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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__asm
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{
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mcr p15, 0, index, c7, c14, 2
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}
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}
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void mmu_invalidate_tlb()
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{
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register rt_uint32_t value;
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value = 0;
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__asm
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{
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mcr p15, 0, value, c8, c7, 0
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}
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}
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void mmu_invalidate_icache()
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{
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register rt_uint32_t value;
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value = 0;
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__asm
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{
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mcr p15, 0, value, c7, c5, 0
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}
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}
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#endif
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void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
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{
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volatile rt_uint32_t *pTT;
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volatile int i,nSec;
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pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
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nSec=(vaddrEnd>>20)-(vaddrStart>>20);
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for(i=0;i<=nSec;i++)
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{
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*pTT = attr |(((paddrStart>>20)+i)<<20);
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pTT++;
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}
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}
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void rt_hw_mmu_init(void)
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{
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int i,j;
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//========================== IMPORTANT NOTE =========================
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//The current stack and code area can't be re-mapped in this routine.
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//If you want memory map mapped freely, your own sophiscated mmu
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//initialization code is needed.
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//===================================================================
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mmu_disable_dcache();
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mmu_disable_icache();
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//If write-back is used,the DCache should be cleared.
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for(i=0;i<64;i++)
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for(j=0;j<8;j++)
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mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
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mmu_invalidate_icache();
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//To complete mmu_Init() fast, Icache may be turned on here.
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mmu_enable_icache();
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mmu_disable();
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mmu_invalidate_tlb();
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//mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
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mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
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mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
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mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
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mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
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mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
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mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
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//mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
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mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
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mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
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//30f00000->30100000, 31000000->30200000
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mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
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mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
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mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
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mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
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mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
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mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
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mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
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mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
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mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
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mmu_setttbase(_MMUTT_STARTADDRESS);
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/* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
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mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
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mmu_enable_alignfault();
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mmu_enable();
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/* ICache enable */
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mmu_enable_icache();
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/* DCache should be turned on after mmu is turned on. */
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mmu_enable_dcache();
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}
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