338 lines
7.6 KiB
C
Executable File
338 lines
7.6 KiB
C
Executable File
/*
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* File : interrupt.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include "at91sam926x.h"
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#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
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extern rt_uint32_t rt_interrupt_nest;
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/* exception and interrupt handler table */
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rt_isr_handler_t isr_table[MAX_HANDLERS];
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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rt_uint32_t at91_extern_irq;
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#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static rt_uint32_t at91sam9260_default_irq_priority[MAX_HANDLERS] = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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0, /* Analog-to-Digital Converter */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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0, /* Multimedia Card Interface */
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2, /* USB Device Port */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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5, /* Serial Synchronous Controller */
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0,
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0,
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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2, /* USB Host port */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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5, /* USART 3 */
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5, /* USART 4 */
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5, /* USART 5 */
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0, /* Timer Counter 3 */
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0, /* Timer Counter 4 */
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0, /* Timer Counter 5 */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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};
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/**
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* @addtogroup AT91SAM926X
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*/
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/*@{*/
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void rt_hw_interrupt_mask(int irq);
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void rt_hw_interrupt_umask(int irq);
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rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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return RT_NULL;
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}
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rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector)
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{
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rt_uint32_t isr, pio, irq_n;
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if (vector == AT91SAM9260_ID_PIOA)
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{
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pio = AT91_PIOA;
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irq_n = AIC_IRQS;
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}
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else if (vector == AT91SAM9260_ID_PIOB)
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{
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pio = AT91_PIOB;
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irq_n = AIC_IRQS + 32;
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}
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else if (vector == AT91SAM9260_ID_PIOC)
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{
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pio = AT91_PIOC;
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irq_n = AIC_IRQS + 32*2;
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}
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else
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return RT_NULL;
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isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR);
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while (isr)
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{
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if (isr & 1)
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{
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isr_table[irq_n](irq_n);
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}
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isr >>= 1;
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irq_n++;
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}
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return RT_NULL;
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}
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/*
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* Initialize the AIC interrupt controller.
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*/
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void at91_aic_init(rt_uint32_t *priority)
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{
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rt_uint32_t i;
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/*
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* The IVR is used by macro get_irqnr_and_base to read and verify.
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* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
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*/
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for (i = 0; i < AIC_IRQS; i++) {
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/* Put irq number in Source Vector Register: */
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at91_sys_write(AT91_AIC_SVR(i), i);
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/* Active Low interrupt, with the specified priority */
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at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
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//AT91_AIC_SRCTYPE_FALLING
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/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
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if (i < 8)
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at91_sys_write(AT91_AIC_EOICR, 0);
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}
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/*
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* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
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* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
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*/
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at91_sys_write(AT91_AIC_SPU, AIC_IRQS);
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/* No debugging in AIC: Debug (Protect) Control Register */
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at91_sys_write(AT91_AIC_DCR, 0);
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/* Disable and clear all interrupts initially */
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at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
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at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
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}
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static void at91_gpio_irq_init()
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{
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at91_sys_write(AT91_PIOA+PIO_IDR, 0xffffffff);
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at91_sys_write(AT91_PIOB+PIO_IDR, 0xffffffff);
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at91_sys_write(AT91_PIOC+PIO_IDR, 0xffffffff);
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isr_table[AT91SAM9260_ID_PIOA] = (rt_isr_handler_t)at91_gpio_irq_handle;
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isr_table[AT91SAM9260_ID_PIOB] = (rt_isr_handler_t)at91_gpio_irq_handle;
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isr_table[AT91SAM9260_ID_PIOC] = (rt_isr_handler_t)at91_gpio_irq_handle;
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rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
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rt_hw_interrupt_umask(AT91SAM9260_ID_PIOB);
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rt_hw_interrupt_umask(AT91SAM9260_ID_PIOC);
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}
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/**
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* This function will initialize hardware interrupt
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*/
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void rt_hw_interrupt_init(void)
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{
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rt_int32_t i;
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register rt_uint32_t idx;
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rt_uint32_t *priority = at91sam9260_default_irq_priority;
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at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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| (1 << AT91SAM9260_ID_IRQ2);
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* init exceptions table */
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for(idx=0; idx < MAX_HANDLERS; idx++)
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{
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isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handle;
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}
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at91_gpio_irq_init();
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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static void at91_gpio_irq_mask(int irq)
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{
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rt_uint32_t pin, pio, bank;
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bank = (irq - AIC_IRQS)>>5;
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if (bank == 0)
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{
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pio = AT91_PIOA;
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}
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else if (bank == 1)
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{
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pio = AT91_PIOB;
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}
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else if (bank == 2)
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{
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pio = AT91_PIOC;
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}
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else
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return;
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pin = 1 << ((irq - AIC_IRQS) & 31);
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at91_sys_write(pio+PIO_IDR, pin);
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int irq)
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{
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if (irq >= AIC_IRQS)
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{
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at91_gpio_irq_mask(irq);
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}
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else
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{
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/* Disable interrupt on AIC */
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at91_sys_write(AT91_AIC_IDCR, 1 << irq);
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}
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}
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static void at91_gpio_irq_umask(int irq)
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{
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rt_uint32_t pin, pio, bank;
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bank = (irq - AIC_IRQS)>>5;
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if (bank == 0)
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{
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pio = AT91_PIOA;
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}
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else if (bank == 1)
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{
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pio = AT91_PIOB;
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}
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else if (bank == 2)
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{
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pio = AT91_PIOC;
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}
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else
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return;
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pin = 1 << ((irq - AIC_IRQS) & 31);
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at91_sys_write(pio+PIO_IER, pin);
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}
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/**
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* This function will un-mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_umask(int irq)
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{
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if (irq >= AIC_IRQS)
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{
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at91_gpio_irq_umask(irq);
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}
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else
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{
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/* Enable interrupt on AIC */
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at91_sys_write(AT91_AIC_IECR, 1 << irq);
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}
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}
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/**
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* This function will install a interrupt service routine to a interrupt.
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* @param vector the interrupt number
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* @param new_handler the interrupt service routine to be installed
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* @param old_handler the old interrupt service routine
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*/
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void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
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{
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if(vector < MAX_HANDLERS)
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{
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if (old_handler != RT_NULL) *old_handler = isr_table[vector];
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if (new_handler != RT_NULL) isr_table[vector] = new_handler;
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}
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}
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/*@}*/
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static int at91_aic_set_type(unsigned irq, unsigned type)
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{
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unsigned int smr, srctype;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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srctype = AT91_AIC_SRCTYPE_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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srctype = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_LOW;
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else
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return -1;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_FALLING;
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else
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return -1;
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break;
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default:
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return -1;
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}
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smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
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at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
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return 0;
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}
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