310 lines
17 KiB
C
310 lines
17 KiB
C
/*
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** ###################################################################
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** Processor: PK40X256VLQ100
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** Compilers: ARM Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU ARM C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** Reference manual: K40P144M100SF2RM, Rev. 3, 4 Nov 2010
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** Version: rev. 1.6, 2011-01-14
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**
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** Abstract:
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** Provides a system configuration function and a global variable that contains the system frequency.
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** It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 0.1 (2010-09-29)
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** Initial version
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** - rev. 1.0 (2010-10-15)
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** First public version
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** - rev. 1.1 (2010-10-27)
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** Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
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** ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
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** CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
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** CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
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** CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE.
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** CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx.
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** DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE.
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** DMA - Peripheral base pointer macro renamed from eDMA to DMA.
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** GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
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** LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE.
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** LCD - Peripheral base pointer macro renamed from SLCD to LCD.
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** PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
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** RFSYS - System regfile registers have been added (#MTWX43999)
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** RFVBAT - VBAT regfile registers have been added (#MTWX43999)
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** RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
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** TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
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** USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE.
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** USB - Peripheral base pointer macro renamed from USBOTG0 to USB0.
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** VREF - Peripheral register TRM removed.
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** - rev. 1.2 (2010-11-11)
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** Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
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** CAN - Individual Matching Element Update (IMEU) feature has been removed.
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** CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
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** CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
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** CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
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** NV - Fixed offset address of BACKKEYx, FPROTx registers.
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** TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
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** - rev. 1.3 (2010-11-19)
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** CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed.
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** CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed.
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** - rev. 1.4 (2010-11-30)
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** EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
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** - rev. 1.5 (2010-12-17)
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** AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
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** - rev. 1.6 (2011-01-14)
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** Added BITBAND_REG() macro to provide access to register bits using bit band region.
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**
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** ###################################################################
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*/
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/*! \file MK40N512MD100 */
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/*! \version 1.6 */
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/*! \date 2011-01-14 */
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/*! \brief Device specific configuration file for MK40N512MD100 (implementation file) */
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/*! \detailed Provides a system configuration function and a global variable that contains the system frequency.
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It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device. */
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#include <stdint.h>
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#include "PK40X256VLQ100.h"
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#define DISABLE_WDOG 1
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#define CLOCK_SETUP 1
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/* Predefined clock setups
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0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
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Core clock/Bus clock derived from an internal clock source 32.768kHz
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Core clock = 47.97MHz, BusClock = 47.97MHz
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1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE} mode
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Clock derived from and external crystal 8MHz
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Core clock = 24MHz, BusClock = 24MHz
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2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
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Core clock/Bus clock derived directly from external crystal with no multiplication
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Core clock = 4MHz, BusClock = 4MHz
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*/
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/*----------------------------------------------------------------------------
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Define clock source values
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*----------------------------------------------------------------------------*/
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#if (CLOCK_SETUP == 0)
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#define CPU_XTAL_CLK_HZ 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
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#elif (CLOCK_SETUP == 1)
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#define CPU_XTAL_CLK_HZ 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 24000000u /* Default System clock value */
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#elif (CLOCK_SETUP == 2)
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#define CPU_XTAL_CLK_HZ 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
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#endif /* (CLOCK_SETUP == 2) */
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if (DISABLE_WDOG)
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/* Disable the WDOG module */
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/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
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WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
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/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
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/* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
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WDOG->STCTRLH = (uint16_t)0x01D2u;
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#endif /* (DISABLE_WDOG) */
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/* System clock initialization */
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#if (CLOCK_SETUP == 0)
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/* Switch to FEI Mode */
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/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x06u;
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/* MCG->C2: ??=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x00u;
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/* MCG_C4: DMX32=1,DRST_DRS=1 */
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MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0x40u) | (uint8_t)0xA0u);
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
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MCG->C5 = (uint8_t)0x00u;
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
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}
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while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
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}
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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#elif (CLOCK_SETUP == 1)
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/* Switch to FBE Mode */
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/* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC->CR = (uint8_t)0x00u;
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/* SIM->SOPT2: MCGCLKSEL=0 */
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SIM->SOPT2 &= (uint8_t)~(uint8_t)0x01u;
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/* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x9Au;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
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MCG->C5 = (uint8_t)0x03u;
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/* MCG->C5: PLLCLKEN=1 */
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MCG->C5 |= (uint8_t)0x40u; /* Enable the PLL */
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT_MASK) == 0u) { /* Check that the oscillator is running */
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}
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while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
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}
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while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
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}
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/* Switch to PBE Mode */
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/* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x82u;
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
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MCG->C6 = (uint8_t)0x40u;
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/* Switch to PEE Mode */
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/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x02u;
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
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MCG->C5 = (uint8_t)0x03u;
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/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
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MCG->C6 = (uint8_t)0x40u;
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while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
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}
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while((MCG->S & MCG_S_LOCK_MASK) == 0u) { /* Wait until locked */
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}
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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#elif (CLOCK_SETUP == 2)
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/* Switch to FBE Mode */
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/* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC->CR = (uint8_t)0x00u;
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/* SIM->SOPT2: MCGCLKSEL=0 */
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SIM->SOPT2 &= (uint8_t)~(uint8_t)0x01u;
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/* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (uint8_t)0x9Au;
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
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/* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
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MCG->C5 = (uint8_t)0x00u;
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/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
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MCG->C6 = (uint8_t)0x00u;
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while((MCG->S & MCG_S_OSCINIT_MASK) == 0u) { /* Check that the oscillator is running */
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}
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while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
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}
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while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
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}
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/* Switch to BLPE Mode */
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/* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
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MCG->C2 = (uint8_t)0x24u;
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/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
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#endif /* (CLOCK_SETUP == 2) */
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate (void) {
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uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
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uint8_t Divider;
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if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
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/* Output of FLL or PLL is selected */
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if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
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/* FLL is selected */
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if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
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/* External reference clock is selected */
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if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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} else { /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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} /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
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Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
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MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
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if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) {
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MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
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} /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) */
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} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
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MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
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} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
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/* Select correct multiplier to calculate the MCG output clock */
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switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
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case 0x0u:
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MCGOUTClock *= 640u;
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break;
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case 0x20u:
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MCGOUTClock *= 1280u;
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break;
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case 0x40u:
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MCGOUTClock *= 1920u;
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break;
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case 0x60u:
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MCGOUTClock *= 2560u;
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break;
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case 0x80u:
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MCGOUTClock *= 732u;
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break;
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case 0xA0u:
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MCGOUTClock *= 1464u;
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break;
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case 0xC0u:
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MCGOUTClock *= 2197u;
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break;
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case 0xE0u:
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MCGOUTClock *= 2929u;
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break;
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default:
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break;
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}
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} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
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/* PLL is selected */
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Divider = (1u + (MCG->C5 & MCG_C5_PRDIV_MASK));
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MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
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Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 24u);
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MCGOUTClock *= Divider; /* Calculate the MCG output clock */
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} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
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} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
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/* Internal reference clock is selected */
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if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
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MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
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} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
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MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
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} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
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} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
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/* External reference clock is selected */
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if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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} else { /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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} /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
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} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
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/* Reserved value */
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return;
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} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
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SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
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}
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