rtt-f030/libcpu/risc-v/e310
zhangjun 98a6896cfa remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();
it will lead to interrupt again in interrupt
2017-07-26 16:07:01 +08:00
..
sifive add context_gcc.s 2017-07-17 15:44:00 +08:00
context_gcc.S remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 2017-07-26 16:07:01 +08:00
encoding.h add context_gcc.s 2017-07-17 15:44:00 +08:00
hifive1.h add context_gcc.s 2017-07-17 15:44:00 +08:00
init.c add context_gcc.s 2017-07-17 15:44:00 +08:00
platform.h add context_gcc.s 2017-07-17 15:44:00 +08:00
stack.c deleted: rtthread.s /*just for debug*/ 2017-07-17 16:55:33 +08:00
start_gcc.S remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); 2017-07-26 16:07:01 +08:00