63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef TIMER_H_
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#define TIMER_H_
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#include <rtdef.h>
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void rt_hw_clock_init(void);
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void rt_hw_get_clock(void);
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void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
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void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
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struct fh_clk;
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/*
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void fh_pmu_open(void);
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void fh_pmu_close(void);
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*/
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#define DIFF_SDC_REFCLK_0 (0)
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#define DIFF_SDC_REFCLK_90 (1)
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#define DIFF_SDC_REFCLK_180 (2)
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#define DIFF_SDC_REFCLK_270 (3)
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#define SDC_CLK_PARA_ERROR (0xffff0000)
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#define SDC_CLK_PARA_OK (0)
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void clk_gate(struct fh_clk *p_clk);
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void clk_ungate(struct fh_clk *p_clk);
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struct fh_clk *clk_get(const char *name);
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rt_uint32_t clk_get_rate(struct fh_clk *p_clk);
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void clk_set_rate(struct fh_clk *p_clk,rt_uint32_t rate_value);
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rt_uint32_t sdc_get_phase(struct fh_clk *p_clk);
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rt_uint32_t sdc_set_phase(struct fh_clk *p_clk,rt_uint32_t phase);
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#endif
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