233 lines
6.2 KiB
C
233 lines
6.2 KiB
C
/*
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* Cache operations for the cache instruction.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
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* (C) Copyright 1999 Silicon Graphics, Inc.
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*/
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#ifndef __CACHE_H__
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#define __CACHE_H__
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#define KUSEG 0x00000000
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#define KSEG0 0x80000000
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#define KSEG1 0xa0000000
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#define KSEG2 0xc0000000
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#define KSEG3 0xe0000000
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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#define Index_Load_Tag_I 0x04
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#define Index_Load_Tag_D 0x05
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#define Index_Store_Tag_I 0x08
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#define Index_Store_Tag_D 0x09
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#define Hit_Invalidate_I 0x10
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#define Hit_Invalidate_D 0x11
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#define Hit_Writeback_Inv_D 0x15
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#define Hit_Writeback_I 0x18
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#define Hit_Writeback_D 0x19
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/*
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*The lock state is cleared by executing an Index
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Invalidate, Index Writeback Invalidate, Hit
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Invalidate, or Hit Writeback Invalidate
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operation to the locked line, or via an Index
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Store Tag operation with the lock bit reset in
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the TagLo register.
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*/
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#define Fetch_And_Lock_I 0x1c
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#define Fetch_And_Lock_D 0x1d
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/*
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* R4000-specific cacheops
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*/
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#define Create_Dirty_Excl_D 0x0d
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#define Fill 0x14
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/*
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* R4000SC and R4400SC-specific cacheops
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*/
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#define Index_Invalidate_SI 0x02
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#define Index_Writeback_Inv_SD 0x03
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#define Index_Load_Tag_SI 0x06
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#define Index_Load_Tag_SD 0x07
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#define Index_Store_Tag_SI 0x0A
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#define Index_Store_Tag_SD 0x0B
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#define Create_Dirty_Excl_SD 0x0f
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#define Hit_Invalidate_SI 0x12
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#define Hit_Invalidate_SD 0x13
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#define Hit_Writeback_Inv_SD 0x17
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#define Hit_Writeback_SD 0x1b
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#define Hit_Set_Virtual_SI 0x1e
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#define Hit_Set_Virtual_SD 0x1f
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/*
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* R5000-specific cacheops
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*/
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#define R5K_Page_Invalidate_S 0x17
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/*
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* RM7000-specific cacheops
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*/
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#define Page_Invalidate_T 0x16
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/*
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* R1000-specific cacheops
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*
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* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
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* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
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*/
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#define Index_Writeback_Inv_S 0x03
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#define Index_Load_Tag_S 0x07
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#define Index_Store_Tag_S 0x0B
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#define Hit_Invalidate_S 0x13
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#define Cache_Barrier 0x14
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#define Hit_Writeback_Inv_S 0x17
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#define Index_Load_Data_I 0x18
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#define Index_Load_Data_D 0x19
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#define Index_Load_Data_S 0x1b
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#define Index_Store_Data_I 0x1c
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#define Index_Store_Data_D 0x1d
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#define Index_Store_Data_S 0x1f
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#ifndef __ASSEMBLER__
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#ifndef dcache_size
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#define dcache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
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#endif
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#ifndef icache_size
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#define icache_size (g_mips_core.dcache_ways * g_mips_core.dcache_lines_per_way * g_mips_core.dcache_line_size)
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#endif
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#ifndef cpu_dcache_line_size
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#define cpu_dcache_line_size() g_mips_core.icache_line_size
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#endif
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#ifndef cpu_icache_line_size
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#define cpu_icache_line_size() g_mips_core.icache_line_size
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#endif
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set mips0 \n" \
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" .set reorder" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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#define cache16_unroll32(base, op) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
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" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
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" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
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" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
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" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
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" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
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" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
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" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
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" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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: \
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: "r" (base), \
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"i" (op));
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static inline void flush_icache_line_indexed(rt_ubase_t addr)
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{
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cache_op(Index_Invalidate_I, addr);
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}
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static inline void flush_dcache_line_indexed(rt_ubase_t addr)
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{
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cache_op(Index_Writeback_Inv_D, addr);
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}
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static inline void flush_icache_line(rt_ubase_t addr)
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{
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cache_op(Hit_Invalidate_I, addr);
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}
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static inline void lock_icache_line(rt_ubase_t addr)
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{
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cache_op(Fetch_And_Lock_I, addr);
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}
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static inline void lock_dcache_line(rt_ubase_t addr)
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{
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cache_op(Fetch_And_Lock_D, addr);
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}
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static inline void flush_dcache_line(rt_ubase_t addr)
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{
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void invalidate_dcache_line(rt_ubase_t addr)
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{
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cache_op(Hit_Invalidate_D, addr);
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}
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static inline void blast_dcache16(void)
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{
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rt_ubase_t start = KSEG0;
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rt_ubase_t end = start + dcache_size;
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rt_ubase_t addr;
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr, Index_Writeback_Inv_D);
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}
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static inline void inv_dcache16(void)
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{
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rt_ubase_t start = KSEG0;
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rt_ubase_t end = start + dcache_size;
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rt_ubase_t addr;
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr, Hit_Invalidate_D);
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}
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static inline void blast_icache16(void)
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{
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rt_ubase_t start = KSEG0;
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rt_ubase_t end = start + icache_size;
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rt_ubase_t addr;
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr, Index_Invalidate_I);
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}
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void r4k_cache_init(void);
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void r4k_cache_flush_all(void);
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void r4k_icache_flush_all(void);
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void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
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void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
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void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
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void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
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#endif /*end of __ASSEMBLER__ */
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#endif /* end of __CACHE_H__ */
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