713 lines
16 KiB
C
713 lines
16 KiB
C
/*
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* File : dm9161.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include "dm9161.h"
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#include <sep4020.h>
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#include "mii.h"
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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/*
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* Davicom dm9161EP driver
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*
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* IRQ_LAN connects to EINT7(GPF7)
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* nLAN_CS connects to nGCS4
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*/
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/* #define dm9161_DEBUG 1 */
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#if DM9161_DEBUG
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#define DM9161_TRACE rt_kprintf
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#else
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#define DM9161_TRACE(...)
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#endif
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/*
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* dm9161 interrupt line is connected to PF7
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*/
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//--------------------------------------------------------
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#define DM9161_PHY 0x40 /* PHY address 0x01 */
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#define MAX_ADDR_LEN 6
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enum DM9161_PHY_mode
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{
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DM9161_10MHD = 0, DM9161_100MHD = 1,
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DM9161_10MFD = 4, DM9161_100MFD = 5,
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DM9161_AUTO = 8, DM9161_1M_HPNA = 0x10
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};
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enum DM9161_TYPE
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{
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TYPE_DM9161,
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};
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struct rt_dm9161_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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enum DM9161_TYPE type;
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enum DM9161_PHY_mode mode;
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rt_uint8_t imr_all;
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rt_uint8_t phy_addr;
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rt_uint32_t tx_index;
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rt_uint8_t packet_cnt; /* packet I or II */
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rt_uint16_t queue_packet_len; /* queued packet (packet II) */
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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static struct rt_dm9161_eth dm9161_device;
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static struct rt_semaphore sem_ack, sem_lock;
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void rt_dm9161_isr(int irqno);
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static void udelay(unsigned long ns)
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{
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unsigned long i;
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while (ns--)
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{
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i = 100;
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while (i--);
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}
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}
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static __inline unsigned long sep_emac_read(unsigned int reg)
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{
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void __iomem *emac_base = (void __iomem *)reg;
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return read_reg(emac_base);
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}
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/*
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* Write to a EMAC register.
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*/
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static __inline void sep_emac_write(unsigned int reg, unsigned long value)
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{
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void __iomem *emac_base = (void __iomem *)reg;
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write_reg(emac_base,value);
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}
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/* ........................... PHY INTERFACE ........................... */
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/* CAN DO MAC CONFIGRATION
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* Enable the MDIO bit in MAC control register
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* When not called from an interrupt-handler, access to the PHY must be
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* protected by a spinlock.
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*/
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static void enable_mdi(void) //need think more
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{
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unsigned long ctl;
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ctl = sep_emac_read(MAC_CTRL);
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sep_emac_write(MAC_CTRL, ctl&(~0x3)); /* enable management port */
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return;
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}
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/* CANNOT DO MAC CONFIGRATION
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* Disable the MDIO bit in the MAC control register
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*/
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static void disable_mdi(void)
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{
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unsigned long ctl;
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ctl = sep_emac_read(MAC_CTRL);
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sep_emac_write(MAC_CTRL, ctl|(0x3)); /* disable management port */
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return;
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}
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/*
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* Wait until the PHY operation is complete.
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*/
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static __inline void sep_phy_wait(void)
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{
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unsigned long timeout = 2;
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while ((sep_emac_read(MAC_MII_STATUS) & 0x2))
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{
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timeout--;
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if (!timeout)
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{
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EOUT("sep_ether: MDIO timeout\n");
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break;
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}
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}
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return;
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}
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/*
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* Write value to the a PHY register
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* Note: MDI interface is assumed to already have been enabled.
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*/
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static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
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{
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unsigned short mii_txdata;
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mii_txdata = value;
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sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr);
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sep_emac_write(MAC_MII_TXDATA ,mii_txdata);
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sep_emac_write(MAC_MII_CMD ,0x4);
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udelay(40);
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sep_phy_wait();
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return;
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}
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/*
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* Read value stored in a PHY register.
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* Note: MDI interface is assumed to already have been enabled.
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*/
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static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
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{
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unsigned short mii_rxdata;
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// unsigned long mii_status;
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sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr);
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sep_emac_write(MAC_MII_CMD ,0x2);
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udelay(40);
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sep_phy_wait();
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mii_rxdata = sep_emac_read(MAC_MII_RXDATA);
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*value = mii_rxdata;
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return;
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}
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/* interrupt service routine */
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void rt_dm9161_isr(int irqno)
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{
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unsigned long intstatus;
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rt_uint32_t address;
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mask_irq(INTSRC_MAC);
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intstatus = sep_emac_read(MAC_INTSRC);
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sep_emac_write(MAC_INTSRC,intstatus);
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/*Receive complete*/
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if(intstatus & 0x04)
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{
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eth_device_ready(&(dm9161_device.parent));
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}
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/*Receive error*/
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else if(intstatus & 0x08)
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{
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rt_kprintf("Receive error\n");
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}
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/*Transmit complete*/
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else if(intstatus & 0x03)
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{
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if(dm9161_device.tx_index == 0)
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address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8);
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else if(dm9161_device.tx_index == 1)
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address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8);
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else
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address = (MAC_TX_BD + dm9161_device.tx_index*8-16);
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//printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex);
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sep_emac_write(address,0x0);
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}
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else if (intstatus & 0x10)
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{
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rt_kprintf("ROVER ERROR\n");
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}
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while(intstatus)
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{
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sep_emac_write(MAC_INTSRC,intstatus);
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intstatus = sep_emac_read(MAC_INTSRC);
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}
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unmask_irq(INTSRC_MAC);
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}
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static rt_err_t update_mac_address()
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{
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rt_uint32_t lo,hi;
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hi = sep_emac_read(MAC_ADDR1);
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lo = sep_emac_read(MAC_ADDR0);
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DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo);
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sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5]));
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sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8));
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hi = sep_emac_read(MAC_ADDR1);
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lo = sep_emac_read(MAC_ADDR0);
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DBOUT("After MAC: hi=%x lo=%x\n",hi,lo);
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return RT_EOK;
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}
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static int mii_link_ok(unsigned long phy_id)
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{
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/* first, a dummy read, needed to latch some MII phys */
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unsigned int value;
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read_phy(phy_id, MII_BMSR,&value);
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if (value & BMSR_LSTATUS)
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return 1;
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return 0;
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}
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static void update_link_speed(unsigned short phy_addr)
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{
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unsigned int bmsr, bmcr, lpa, mac_cfg;
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unsigned int speed, duplex;
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if (!mii_link_ok(phy_addr))
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{
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EOUT("Link Down\n");
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//goto result;
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}
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read_phy(phy_addr,MII_BMSR,&bmsr);
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read_phy(phy_addr,MII_BMCR,&bmcr);
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if (bmcr & BMCR_ANENABLE) /* AutoNegotiation is enabled */
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{
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if (!(bmsr & BMSR_ANEGCOMPLETE)) /* Do nothing - another interrupt generated when negotiation complete */
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goto result;
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read_phy(phy_addr, MII_LPA, &lpa);
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if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
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speed = SPEED_100;
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else
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speed = SPEED_10;
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if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
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duplex = DUPLEX_FULL;
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else
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duplex = DUPLEX_HALF;
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}
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else
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{
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speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
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duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
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}
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/* Update the MAC */
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mac_cfg = sep_emac_read(MAC_CTRL);
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if (speed == SPEED_100)
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{
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mac_cfg |= 0x800; /* set speed 100 M */
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//bmcr &=(~0x2000);
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//write_phy(lp->phy_address, MII_BMCR, bmcr); //<2F><>dm9161<36><31><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD>Ϊ10M
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if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
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mac_cfg |= 0x400;
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else /* 100 Half Duplex */
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mac_cfg &= (~0x400);
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}
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else
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{
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mac_cfg &= (~0x800); /* set speed 10 M */
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if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
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mac_cfg |= 0x400;
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else /* 10 Half Duplex */
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mac_cfg &= (~0x400);
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}
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sep_emac_write(MAC_CTRL, mac_cfg);
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rt_kprintf("Link now %i M-%s\n", speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
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result:
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mac_cfg = sep_emac_read(MAC_CTRL);
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DBOUT("After mac_cfg=%d\n",mac_cfg);
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return;
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}
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static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag);
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/* RT-Thread Device Interface */
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/* initialize the interface */
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static rt_err_t rt_dm9161_init(rt_device_t dev)
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{
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unsigned int phyid1, phyid2;
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int detected = -1;
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unsigned long phy_id;
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unsigned short phy_address = 0;
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while ((detected != 0) && (phy_address < 32))
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{
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/* Read the PHY ID registers */
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enable_mdi();
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read_phy(phy_address, MII_PHYSID1, &phyid1);
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read_phy(phy_address, MII_PHYSID2, &phyid2);
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disable_mdi();
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phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
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switch (phy_id)
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{
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case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
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case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
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case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
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case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
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case MII_DP83847_ID: /* National Semiconductor DP83847: */
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case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
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case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
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{
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enable_mdi();
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#warning SHOULD SET MAC ADDR
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//get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
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update_mac_address(); /* Program ethernet address into MAC */
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//<2F>ù<EFBFBD>ϣ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>Ƚϵ<C8BD>ǰȺ<C7B0><C8BA><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ȫ˫<C8AB><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CRCУ<43>飬<EFBFBD><E9A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡<EFBFBD><D6A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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sep_emac_write(MAC_CTRL, 0xa413);
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#warning SHOULD DETERMIN LINK SPEED
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update_link_speed(phy_address);
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dm9161_device.phy_addr = phy_address;
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disable_mdi();
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break;
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}
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}
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phy_address++;
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}
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rt_dm9161_open(dev,0);
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return RT_EOK;
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}
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/* ................................ MAC ................................ */
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/*
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* Initialize and start the Receiver and Transmit subsystems
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*/
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static void sepether_start(void)
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{
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int i;
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unsigned int tempaddr;
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sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR);
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//<2F><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ͺͽ<CDBA><CDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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for (i = 0; i < MAX_TX_DESCR; i++)
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{
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tempaddr=(MAC_TX_BD+i*8);
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sep_emac_write(tempaddr,0);
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tempaddr=(MAC_TX_BD+i*8+4);
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sep_emac_write(tempaddr,0);
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}
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for (i = 0; i < MAX_RX_DESCR; i++)
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{
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tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8);
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sep_emac_write(tempaddr,0);
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tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4);
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sep_emac_write(tempaddr,0);
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}
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for (i = 0; i < MAX_RX_DESCR; i++)
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{
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tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8);
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sep_emac_write(tempaddr,0xc000);
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tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4);
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sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600);
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}
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/* Set the Wrap bit on the last descriptor */
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tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8);
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sep_emac_write(tempaddr,0xe000);
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for (i = 0; i < MAX_TX_DESCR; i++)
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{
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tempaddr=(MAC_TX_BD+i*8);
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sep_emac_write(tempaddr,0x0);
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tempaddr=(MAC_TX_BD+i*8+4);
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sep_emac_write(tempaddr,ESRAM_BASE+i*0x600);
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}
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return;
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}
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static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag)
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{
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unsigned int dsintr;
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enable_mdi();
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mask_irq(28);
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sep_emac_write(MAC_INTMASK,0x0); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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sepether_start();
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/* Enable PHY interrupt */
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*(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ; //1 stands for in
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*(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ; //for common use
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*(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080; //<2F>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>뷽ʽ
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*(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14); //<2F>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>͵<EFBFBD>ƽ<EFBFBD>ⷢ
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*(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080; //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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*(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000; //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
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rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL);
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enable_irq(INTSRC_EXINT7);
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read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr);
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dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
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write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr);
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update_link_speed(dm9161_device.phy_addr);
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/************************************************************************************/
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/* Enable MAC interrupts */
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sep_emac_write(MAC_INTMASK,0xff); //open<65>ж<EFBFBD>
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sep_emac_write(MAC_INTSRC,0xff); //clear all mac irq
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unmask_irq(28);
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disable_mdi();
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rt_kprintf("SEP4020 ethernet interface open!\n\r");
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return RT_EOK;
|
||
}
|
||
|
||
static rt_err_t rt_dm9161_close(rt_device_t dev)
|
||
{
|
||
rt_kprintf("SEP4020 ethernet interface close!\n\r");
|
||
|
||
/* Disable Receiver and Transmitter */
|
||
disable_mdi();
|
||
#warning disable ether;
|
||
|
||
// INT_ENABLE(28);
|
||
/* Disable PHY interrupt */
|
||
// disable_phyirq(dev);
|
||
|
||
/* Disable MAC interrupts */
|
||
sep_emac_write(MAC_INTMASK,0); //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||
|
||
// INT_DISABLE(28);
|
||
|
||
return RT_EOK;
|
||
}
|
||
|
||
static rt_size_t rt_dm9161_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||
{
|
||
rt_set_errno(-RT_ENOSYS);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static rt_size_t rt_dm9161_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||
{
|
||
rt_set_errno(-RT_ENOSYS);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static rt_err_t rt_dm9161_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||
{
|
||
return RT_EOK;
|
||
}
|
||
|
||
/* ethernet device interface */
|
||
/* transmit packet. */
|
||
rt_err_t rt_dm9161_tx( rt_device_t dev, struct pbuf* p)
|
||
{
|
||
rt_uint8_t i;
|
||
rt_uint32_t length = 0;
|
||
struct pbuf *q;
|
||
unsigned long address;
|
||
unsigned long tmp_tx_bd;
|
||
|
||
/* lock DM9000 device */
|
||
// rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
||
|
||
/* disable dm9000a interrupt */
|
||
#warning SHOULD DISABLE INTEERUPT?
|
||
|
||
/*Search for available BD*/
|
||
for (i = 0;i<MAX_TX_DESCR;)
|
||
{
|
||
address = MAC_TX_BD + i*8;
|
||
tmp_tx_bd = sep_emac_read(address);
|
||
if (!(tmp_tx_bd & 0x8000))
|
||
{
|
||
if (i == (MAX_TX_DESCR-1))
|
||
i = 0;
|
||
else
|
||
i = i+1;
|
||
break;
|
||
}
|
||
if (i == MAX_TX_DESCR-1)
|
||
i = 0;
|
||
else
|
||
i++;
|
||
}
|
||
|
||
q = p;
|
||
while (q)
|
||
{
|
||
rt_memcpy((u8_t*)(ESRAM_BASE + i*0x600 + length),(u8_t*)q->payload,q->len);
|
||
length += q->len;
|
||
q = q->next;
|
||
}
|
||
|
||
#warning SHOULD NOTICE IT'S LENGTH
|
||
|
||
length = length << 16;
|
||
|
||
if (i == MAX_TX_DESCR - 1)
|
||
length |= 0xb800;
|
||
else
|
||
length |= 0x9800;
|
||
|
||
address = (MAC_TX_BD + i*8);
|
||
dm9161_device.tx_index = i;
|
||
sep_emac_write(address,length);
|
||
|
||
//wait for tranfer complete
|
||
while(!(sep_emac_read(address)&0x8000));
|
||
|
||
/* unlock DM9000 device */
|
||
// rt_sem_release(&sem_lock);
|
||
|
||
/* wait ack */
|
||
// rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
|
||
|
||
return RT_EOK;
|
||
}
|
||
|
||
/* reception packet. */
|
||
struct pbuf *rt_dm9161_rx(rt_device_t dev)
|
||
{
|
||
unsigned int temp_rx_bd,address;
|
||
rt_uint32_t i = 0;
|
||
rt_uint32_t length;
|
||
unsigned char *p_recv;
|
||
struct pbuf* p = RT_NULL;
|
||
|
||
/* lock DM9000 device */
|
||
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
|
||
|
||
while (1)
|
||
{
|
||
|
||
address = MAC_TX_BD + (MAX_TX_DESCR + i) * 8;
|
||
temp_rx_bd = sep_emac_read(address);
|
||
|
||
if (!(temp_rx_bd & 0x8000))
|
||
{
|
||
length = temp_rx_bd;
|
||
length = length >> 16;
|
||
|
||
p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600);
|
||
p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM);
|
||
if (p != RT_NULL)
|
||
{
|
||
struct pbuf *q;
|
||
rt_int32_t len;
|
||
|
||
for (q = p; q != RT_NULL; q = q->next)
|
||
{
|
||
rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
rt_kprintf("Droping %d packet \n",length);
|
||
}
|
||
|
||
if(i == (MAX_RX_DESCR-1))
|
||
{
|
||
sep_emac_write(address,0xe000);
|
||
i = 0;
|
||
}
|
||
else
|
||
{
|
||
sep_emac_write(address,0xc000);
|
||
i++;
|
||
}
|
||
}
|
||
else
|
||
break;
|
||
}
|
||
|
||
rt_sem_release(&sem_lock);
|
||
|
||
return p;
|
||
}
|
||
|
||
void rt_hw_dm9161_init()
|
||
{
|
||
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
||
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
||
|
||
dm9161_device.type = TYPE_DM9161;
|
||
dm9161_device.mode = DM9161_AUTO;
|
||
dm9161_device.packet_cnt = 0;
|
||
dm9161_device.queue_packet_len = 0;
|
||
|
||
/*
|
||
* SRAM Tx/Rx pointer automatically return to start address,
|
||
* Packet Transmitted, Packet Received
|
||
*/
|
||
#warning NOTICE:
|
||
//dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
|
||
|
||
dm9161_device.dev_addr[0] = 0x01;
|
||
dm9161_device.dev_addr[1] = 0x60;
|
||
dm9161_device.dev_addr[2] = 0x6E;
|
||
dm9161_device.dev_addr[3] = 0x11;
|
||
dm9161_device.dev_addr[4] = 0x02;
|
||
dm9161_device.dev_addr[5] = 0x0F;
|
||
|
||
dm9161_device.parent.parent.init = rt_dm9161_init;
|
||
dm9161_device.parent.parent.open = rt_dm9161_open;
|
||
dm9161_device.parent.parent.close = rt_dm9161_close;
|
||
dm9161_device.parent.parent.read = rt_dm9161_read;
|
||
dm9161_device.parent.parent.write = rt_dm9161_write;
|
||
dm9161_device.parent.parent.control = rt_dm9161_control;
|
||
dm9161_device.parent.parent.user_data = RT_NULL;
|
||
|
||
dm9161_device.parent.eth_rx = rt_dm9161_rx;
|
||
dm9161_device.parent.eth_tx = rt_dm9161_tx;
|
||
|
||
eth_device_init(&(dm9161_device.parent), "e0");
|
||
|
||
/* instal interrupt */
|
||
#warning TODO
|
||
//rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL);
|
||
//rt_hw_interrupt_umask(INTEINT4_7);
|
||
}
|
||
|
||
void dm9161a(void)
|
||
{
|
||
}
|
||
|
||
#ifdef RT_USING_FINSH
|
||
#include <finsh.h>
|
||
FINSH_FUNCTION_EXPORT(dm9161a, dm9161a register dump);
|
||
#endif
|