315 lines
11 KiB
C
315 lines
11 KiB
C
/******************************************************************************
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**
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** \file gh_timer.c
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**
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** \brief TIMER.
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**
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** Copyright: 2012 - 2016 (C) GoKe Microelectronics
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef SRC_INLINE
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#include "gh_timer.h"
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_TIMER_CNTNSTS_REAL FIO_ADDRESS(TIMER,0x7000B000) /* read/write */
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#define REG_TIMER_RELOADN_REAL FIO_ADDRESS(TIMER,0x7000B004) /* read/write */
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#define REG_TIMER_MATCH1_REAL FIO_ADDRESS(TIMER,0x7000B008) /* read/write */
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#define REG_TIMER_MATCH2_REAL FIO_ADDRESS(TIMER,0x7000B00C) /* read/write */
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#define REG_TIMER_CONTROL_REAL FIO_ADDRESS(TIMER,0x7000B030) /* read/write */
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* TIMER_Control */
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U32 all;
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struct {
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U32 enable1 : 1;
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U32 clksel1 : 1;
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U32 of1 : 1;
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U32 : 1;
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U32 enable2 : 1;
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U32 clksel2 : 1;
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U32 of2 : 1;
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U32 : 1;
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U32 enable3 : 1;
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U32 clksel3 : 1;
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U32 of3 : 1;
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U32 : 21;
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} bitc;
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} GH_TIMER_CONTROL_REAL_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* register TIMER_CntnSts (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_TIMER_set_CntnSts(U8 index, U32 data)
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{
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*(volatile U32 *)(REG_TIMER_CNTNSTS_REAL + index * FIO_MOFFSET(TIMER,0x00000010)) = data;
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}
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GH_INLINE U32 GH_TIMER_get_CntnSts(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_TIMER_CNTNSTS_REAL + index * FIO_MOFFSET(TIMER,0x00000010)));
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return value;
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}
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/*----------------------------------------------------------------------------*/
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/* register TIMER_Reloadn (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_TIMER_set_Reloadn(U8 index, U32 data)
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{
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*(volatile U32 *)(REG_TIMER_RELOADN_REAL + index * FIO_MOFFSET(TIMER,0x00000010)) = data;
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}
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GH_INLINE U32 GH_TIMER_get_Reloadn(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_TIMER_RELOADN_REAL + index * FIO_MOFFSET(TIMER,0x00000010)));
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return value;
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}
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/*----------------------------------------------------------------------------*/
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/* register TIMER_Match1 (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_TIMER_set_Match1(U8 index, U32 data)
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{
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*(volatile U32 *)(REG_TIMER_MATCH1_REAL + index * FIO_MOFFSET(TIMER,0x00000010)) = data;
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}
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GH_INLINE U32 GH_TIMER_get_Match1(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_TIMER_MATCH1_REAL + index * FIO_MOFFSET(TIMER,0x00000010)));
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return value;
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}
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/*----------------------------------------------------------------------------*/
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/* register TIMER_Match2 (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_TIMER_set_Match2(U8 index, U32 data)
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{
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*(volatile U32 *)(REG_TIMER_MATCH2_REAL + index * FIO_MOFFSET(TIMER,0x00000010)) = data;
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}
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GH_INLINE U32 GH_TIMER_get_Match2(U8 index)
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{
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U32 value = (*(volatile U32 *)(REG_TIMER_MATCH2_REAL + index * FIO_MOFFSET(TIMER,0x00000010)));
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return value;
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}
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/*----------------------------------------------------------------------------*/
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/* register TIMER_Control (read/write) */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_TIMER_set_Control(U32 data)
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{
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GH_TIMER_CONTROL_REAL_S real;
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GH_TIMER_CONTROL_S dummy;
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dummy.all = data ;
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real.bitc.enable1 = dummy.bitc.enable1;
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real.bitc.clksel1 = dummy.bitc.clksel1;
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real.bitc.of1 = dummy.bitc.of1;
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real.bitc.enable2 = dummy.bitc.enable2;
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real.bitc.clksel2 = dummy.bitc.clksel2;
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real.bitc.of2 = dummy.bitc.of2;
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real.bitc.enable3 = dummy.bitc.enable3;
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real.bitc.clksel3 = dummy.bitc.clksel3;
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real.bitc.of3 = dummy.bitc.of3;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = real.all;
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}
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GH_INLINE U32 GH_TIMER_get_Control(void)
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{
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GH_TIMER_CONTROL_REAL_S real;
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GH_TIMER_CONTROL_S dummy;
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dummy.all = 0;
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real.all = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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dummy.bitc.enable1 = real.bitc.enable1;
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dummy.bitc.clksel1 = real.bitc.clksel1;
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dummy.bitc.of1 = real.bitc.of1;
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dummy.bitc.enable2 = real.bitc.enable2;
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dummy.bitc.clksel2 = real.bitc.clksel2;
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dummy.bitc.of2 = real.bitc.of2;
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dummy.bitc.enable3 = real.bitc.enable3;
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dummy.bitc.clksel3 = real.bitc.clksel3;
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dummy.bitc.of3 = real.bitc.of3;
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return dummy.all;
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}
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GH_INLINE void GH_TIMER_set_Control_Enable1(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.enable1 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_Enable1(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.enable1;
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}
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GH_INLINE void GH_TIMER_set_Control_ClkSel1(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.clksel1 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_ClkSel1(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.clksel1;
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}
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GH_INLINE void GH_TIMER_set_Control_OF1(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.of1 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_OF1(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.of1;
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}
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GH_INLINE void GH_TIMER_set_Control_Enable2(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.enable2 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_Enable2(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.enable2;
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}
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GH_INLINE void GH_TIMER_set_Control_ClkSel2(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.clksel2 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_ClkSel2(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.clksel2;
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}
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GH_INLINE void GH_TIMER_set_Control_OF2(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.of2 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_OF2(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.of2;
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}
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GH_INLINE void GH_TIMER_set_Control_Enable3(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.enable3 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_Enable3(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.enable3;
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}
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GH_INLINE void GH_TIMER_set_Control_ClkSel3(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.clksel3 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_ClkSel3(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.clksel3;
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}
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GH_INLINE void GH_TIMER_set_Control_OF3(U8 data)
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{
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GH_TIMER_CONTROL_REAL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL_REAL;
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d.bitc.of3 = data;
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*(volatile U32 *)REG_TIMER_CONTROL_REAL = d.all;
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}
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GH_INLINE U8 GH_TIMER_get_Control_OF3(void)
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{
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GH_TIMER_CONTROL_REAL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL_REAL);
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tmp_value.all = value;
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return tmp_value.bitc.of3;
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}
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/*----------------------------------------------------------------------------*/
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/* init function */
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/*----------------------------------------------------------------------------*/
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GH_INLINE void GH_TIMER_init(void)
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{
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int i;
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for (i=0; i<3; i++)
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{
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GH_TIMER_set_CntnSts(i, (U32)0x00000000);
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}
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for (i=0; i<3; i++)
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{
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GH_TIMER_set_Reloadn(i, (U32)0x00000000);
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}
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for (i=0; i<3; i++)
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{
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GH_TIMER_set_Match1(i, (U32)0x00000000);
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}
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for (i=0; i<3; i++)
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{
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GH_TIMER_set_Match2(i, (U32)0x00000000);
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}
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GH_TIMER_set_Control((U32)0x00000000);
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/* read read-clear registers in order to set mirror variables */
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}
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/*----------------------------------------------------------------------------*/
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/* end of file */
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/*----------------------------------------------------------------------------*/
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