543 lines
14 KiB
C
543 lines
14 KiB
C
/*
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* File : stm32f1_i2c.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2017, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-07-04 aubrcool@qq.com 1st version
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*/
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#include "stm32f10x.h"
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#include "stm32f1_i2c.h"
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#include <rtdevice.h>
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#ifdef RT_USING_I2C
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/* I2C SPE mask */
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#define CR1_PE_Set ((uint16_t)0x0001)
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#define CR1_PE_Reset ((uint16_t)0xFFFE)
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/* I2C START mask */
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#define CR1_START_Set ((uint16_t)0x0100)
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#define CR1_START_Reset ((uint16_t)0xFEFF)
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/* I2C STOP mask */
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#define CR1_STOP_Set ((uint16_t)0x0200)
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#define CR1_STOP_Reset ((uint16_t)0xFDFF)
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/* I2C ACK mask */
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#define CR1_ACK_Set ((uint16_t)0x0400)
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#define CR1_ACK_Reset ((uint16_t)0xFBFF)
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/* I2C ENGC mask */
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#define CR1_ENGC_Set ((uint16_t)0x0040)
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#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
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/* I2C SWRST mask */
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#define CR1_SWRST_Set ((uint16_t)0x8000)
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#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
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/* I2C PEC mask */
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#define CR1_PEC_Set ((uint16_t)0x1000)
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#define CR1_PEC_Reset ((uint16_t)0xEFFF)
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/* I2C ENPEC mask */
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#define CR1_ENPEC_Set ((uint16_t)0x0020)
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#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
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/* I2C ENARP mask */
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#define CR1_ENARP_Set ((uint16_t)0x0010)
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#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
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/* I2C NOSTRETCH mask */
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#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
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#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
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/* I2C registers Masks */
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#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
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/* I2C DMAEN mask */
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#define CR2_DMAEN_Set ((uint16_t)0x0800)
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#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
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/* I2C LAST mask */
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#define CR2_LAST_Set ((uint16_t)0x1000)
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#define CR2_LAST_Reset ((uint16_t)0xEFFF)
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/* I2C FREQ mask */
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#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
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/* I2C ADD0 mask */
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#define OAR1_ADD0_Set ((uint16_t)0x0001)
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#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
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/* I2C ENDUAL mask */
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#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
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#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
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/* I2C ADD2 mask */
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#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
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/* I2C F/S mask */
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#define CCR_FS_Set ((uint16_t)0x8000)
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/* I2C CCR mask */
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#define CCR_CCR_Set ((uint16_t)0x0FFF)
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/* I2C FLAG mask */
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#define FLAG_Mask ((uint32_t)0x00FFFFFF)
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/* I2C Interrupt Enable mask */
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#define ITEN_Mask ((uint32_t)0x07000000)
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#define I2CADDR 0x0A
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enum
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{
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EV_END = 0,
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};
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#ifdef RT_USING_I2C1
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static struct stm32_i2c_bus stm32_i2c1 =
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{
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.I2C = I2C1,
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};
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#endif /*RT_USING_I2C1*/
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#ifdef RT_USING_I2C2
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static struct stm32_i2c_bus stm32_i2c2 =
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{
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.I2C = I2C2,
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};
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#endif /*RT_USING_I2C2*/
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rt_inline rt_err_t stm32_i2c_wait_ev(struct stm32_i2c_bus *bus,
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rt_uint32_t ev, rt_uint32_t timeout)
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{
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rt_uint32_t res = 0;
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rt_event_recv(&bus->ev, 0x01 << ev,
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RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
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timeout, &res);
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if(res != ev)
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{
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return RT_ERROR;
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}
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else
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{
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return RT_EOK;
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}
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}
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rt_inline void stm32_i2c_send_ev(struct stm32_i2c_bus *bus, rt_uint32_t ev)
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{
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rt_event_send(&bus->ev, 0x01 << ev);
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}
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static rt_size_t stm_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static rt_size_t stm_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static rt_err_t stm_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t,
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rt_uint32_t);
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static const struct rt_i2c_bus_device_ops stm32_i2c_ops =
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{
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stm_i2c_mst_xfer,
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stm_i2c_slv_xfer,
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stm_i2c_bus_control,
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};
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rt_inline void stm32_i2c_disable_nvic(I2C_TypeDef *I2C, rt_uint32_t value)
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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rt_uint32_t evno, erno;
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if(I2C == I2C1)
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{
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evno = I2C1_EV_IRQn;
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erno = I2C1_ER_IRQn;
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}
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else
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{
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evno = I2C2_EV_IRQn;
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erno = I2C2_ER_IRQn;
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}
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NVIC_InitStructure.NVIC_IRQChannel = evno;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 6;
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NVIC_InitStructure.NVIC_IRQChannelCmd = value;
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NVIC_Init(&NVIC_InitStructure);
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NVIC_InitStructure.NVIC_IRQChannel = erno;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 6;
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NVIC_InitStructure.NVIC_IRQChannelCmd = value;
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NVIC_Init(&NVIC_InitStructure);
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}
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static void stm32_i2c_nvic_Config(I2C_TypeDef *I2C)
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{
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stm32_i2c_disable_nvic(I2C, ENABLE);
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}
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static rt_err_t stm_i2c_init(struct rt_i2c_bus_device *bus, rt_uint32_t bitrate)
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{
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struct stm32_i2c_bus *stm32_i2c;
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I2C_InitTypeDef I2C_InitStructure;
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RT_ASSERT(bus != RT_NULL);
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if(bitrate != 100000 && bitrate != 400000)
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{
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return RT_EIO;
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}
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stm32_i2c = (struct stm32_i2c_bus *) bus;
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I2C_Cmd(stm32_i2c->I2C, DISABLE);
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I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
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I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
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I2C_InitStructure.I2C_OwnAddress1 = I2CADDR;
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I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
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I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
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I2C_InitStructure.I2C_ClockSpeed = bitrate;
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I2C_Init(stm32_i2c->I2C, &I2C_InitStructure);
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I2C_Cmd(stm32_i2c->I2C, ENABLE);
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I2C_ITConfig(stm32_i2c->I2C, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR, ENABLE);
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stm32_i2c_nvic_Config(stm32_i2c->I2C);
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return RT_EOK;
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}
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static rt_size_t stm_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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struct stm32_i2c_bus *stm32_i2c;
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rt_uint32_t numbak = num;
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RT_ASSERT(bus != RT_NULL);
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stm32_i2c = (struct stm32_i2c_bus *) bus;
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stm32_i2c->msg = msgs;
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stm32_i2c->msg_ptr = 0;
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stm32_i2c->msg_cnt = num;
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stm32_i2c->dptr = 0;
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stm32_i2c->wait_stop = 0;
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I2C_GetLastEvent(stm32_i2c->I2C);
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while(stm32_i2c->msg_ptr < stm32_i2c->msg_cnt)
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{
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stm32_i2c->wait_stop = 0;
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if(!(stm32_i2c->msg[stm32_i2c->msg_ptr].flags & RT_I2C_NO_START))
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{
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stm32_i2c->I2C->CR1 |= CR1_START_Set;
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}
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stm32_i2c_wait_ev(stm32_i2c, EV_END, 1000);
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}
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stm32_i2c->msg = RT_NULL;
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stm32_i2c->msg_ptr = 0;
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stm32_i2c->msg_cnt = 0;
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stm32_i2c->dptr = 0;
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stm32_i2c->wait_stop = 0;
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return numbak;
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}
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static rt_size_t stm_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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return 0;
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}
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static rt_err_t stm_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t cmd,
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rt_uint32_t arg)
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{
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return RT_ERROR;
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}
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rt_inline void stm32_i2c_ev_handler(struct stm32_i2c_bus *stm32_i2c)
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{
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unsigned int I2C_Event;
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rt_uint8_t data = 0;
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struct rt_i2c_msg *pmsg;
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I2C_Event = I2C_GetLastEvent(stm32_i2c->I2C);
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if(!stm32_i2c->msg)
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{
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return;
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}
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// EV5 0x00030001
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if ((I2C_Event & I2C_EVENT_MASTER_MODE_SELECT) == I2C_EVENT_MASTER_MODE_SELECT)
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{
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// EV5 0x00030001
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pmsg = &stm32_i2c->msg[stm32_i2c->msg_ptr];
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if(pmsg->flags & RT_I2C_ADDR_10BIT)
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{
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data = ((pmsg->addr >> 8) << 1) | 0xF0;
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}
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else
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{
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data = pmsg->addr << 1;
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}
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if(pmsg->flags & RT_I2C_RD)
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{
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data |= 0x01;
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}
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stm32_i2c->I2C->DR = data;
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if(!(pmsg->flags & RT_I2C_RD))
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{
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return;
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}
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if(pmsg->len > 1)
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{
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stm32_i2c->I2C->CR1 |= CR1_ACK_Set;
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return;
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}
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}
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else if((I2C_Event & I2C_EVENT_MASTER_MODE_ADDRESS10) ==
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I2C_EVENT_MASTER_MODE_ADDRESS10)
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{
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// EV9
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data = pmsg->addr & 0xFF;
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stm32_i2c->I2C->DR = data;
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}
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else if((I2C_Event & I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) ==
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I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)
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{
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//EVT 6 SEND 0x00070082
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}
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else if ((I2C_Event & I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) ==
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I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED)
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{
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//EVT 6 RECE 0x00030002
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pmsg = &stm32_i2c->msg[stm32_i2c->msg_ptr];
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if(!(pmsg->flags & RT_I2C_RD))
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{
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return;
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}
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if(pmsg->len > 1)
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{
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return;
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}
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if(stm32_i2c->msg_ptr < stm32_i2c->msg_cnt - 1)
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{
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return;
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}
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else if((pmsg[1].flags & RT_I2C_NO_START))
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{
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return;
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}
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stm32_i2c->I2C->CR1 |= CR1_STOP_Set;
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stm32_i2c->I2C->CR1 &= CR1_ACK_Reset;
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}
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else if ((I2C_Event & I2C_EVENT_MASTER_BYTE_RECEIVED) ==
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I2C_EVENT_MASTER_BYTE_RECEIVED)
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{
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// EVT 7 0x00030040
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pmsg = &stm32_i2c->msg[stm32_i2c->msg_ptr];
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if(pmsg->len && (pmsg->flags & RT_I2C_RD))
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{
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pmsg->buf[stm32_i2c->dptr] = stm32_i2c->I2C->DR;
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stm32_i2c->dptr++;
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pmsg->len--;
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}
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if(pmsg->len == 1 && (pmsg->flags & RT_I2C_RD))
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{
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if(stm32_i2c->msg_ptr >= stm32_i2c->msg_cnt - 1)
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{
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stm32_i2c->I2C->CR1 &= CR1_ACK_Reset;
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stm32_i2c->I2C->CR1 |= CR1_STOP_Set;
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}
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else if(!(pmsg[1].flags & RT_I2C_NO_START))
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{
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stm32_i2c->I2C->CR1 &= CR1_ACK_Reset;
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stm32_i2c->I2C->CR1 |= CR1_STOP_Set;
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}
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}
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if(pmsg->len)
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{
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return;
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}
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stm32_i2c->dptr = 0;
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stm32_i2c->msg_ptr++;
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if(stm32_i2c->msg_ptr < stm32_i2c->msg_cnt)
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{
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return;
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}
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stm32_i2c->I2C->CR1 |= CR1_ACK_Set;
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stm32_i2c_send_ev(stm32_i2c, EV_END);
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}
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else if((I2C_Event & I2C_EVENT_MASTER_BYTE_TRANSMITTING) ==
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I2C_EVENT_MASTER_BYTE_TRANSMITTING)
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{
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//EVT8 0x00070080
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if(stm32_i2c->wait_stop == 0xAAAA5555)
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{
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stm32_i2c->wait_stop = 0;
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stm32_i2c->I2C->CR1 |= CR1_STOP_Set;
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stm32_i2c_send_ev(stm32_i2c, EV_END);
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return;
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}
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if(stm32_i2c->wait_stop == 0x5555AAAA)
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{ //restart cond
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stm32_i2c->wait_stop = 0;
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stm32_i2c_send_ev(stm32_i2c, EV_END);
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return;
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}
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pmsg = &stm32_i2c->msg[stm32_i2c->msg_ptr];
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if(!(pmsg->flags & RT_I2C_RD) && pmsg->len)
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{
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stm32_i2c->I2C->DR = pmsg->buf[stm32_i2c->dptr];
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stm32_i2c->dptr++;
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pmsg->len--;
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}
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if(!(pmsg->flags & RT_I2C_RD) && pmsg->len)
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{
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return;
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}
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if(stm32_i2c->msg_ptr < stm32_i2c->msg_cnt - 1 && pmsg->len == 0)
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{
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stm32_i2c->msg_ptr++;
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stm32_i2c->dptr = 0;
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pmsg = &stm32_i2c->msg[stm32_i2c->msg_ptr];
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if(pmsg->flags & RT_I2C_NO_START)
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{
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return;
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}
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else
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{
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stm32_i2c->wait_stop == 0x5555AAAA;
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return;
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}
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}
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if(stm32_i2c->msg_ptr < stm32_i2c->msg_cnt && pmsg->len == 0)
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{
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stm32_i2c->msg_ptr++;
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stm32_i2c->dptr = 0;
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}
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stm32_i2c->wait_stop = 0xAAAA5555;
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}
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}
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#ifdef RT_USING_I2C1
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void I2C1_EV_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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stm32_i2c_ev_handler(&stm32_i2c1);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif /*RT_USING_I2C1*/
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#ifdef RT_USING_I2C2
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void I2C2_EV_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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stm32_i2c_ev_handler(&stm32_i2c2);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif /*RT_USING_I2C2*/
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rt_inline void stm32_i2c_er_handler(struct stm32_i2c_bus *stm32_i2c)
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{
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if (I2C2->SR1 & 1 << 10)
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{
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I2C2->SR1 &= ~(1 << 10);
|
|
}
|
|
if (I2C2->SR1 & 1 << 14)
|
|
{
|
|
I2C2->SR1 &= ~(1 << 14);
|
|
}
|
|
if (I2C2->SR1 & 1 << 11)
|
|
{
|
|
I2C2->SR1 &= ~(1 << 11);
|
|
}
|
|
if (I2C2->SR1 & 1 << 9)
|
|
{
|
|
I2C2->SR1 &= ~(1 << 9);
|
|
}
|
|
if (I2C2->SR1 & 1 << 8)
|
|
{
|
|
I2C2->SR1 &= ~(1 << 8);
|
|
}
|
|
}
|
|
|
|
#ifdef RT_USING_I2C1
|
|
void I2C1_ER_IRQHandler(void) //I2C2 Error Interrupt
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
stm32_i2c_er_handler(&stm32_i2c1);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /*RT_USING_I2C1*/
|
|
|
|
#ifdef RT_USING_I2C2
|
|
void I2C2_ER_IRQHandler(void) //I2C2 Error Interrupt
|
|
{
|
|
/* enter interrupt */
|
|
rt_interrupt_enter();
|
|
|
|
stm32_i2c_er_handler(&stm32_i2c2);
|
|
|
|
/* leave interrupt */
|
|
rt_interrupt_leave();
|
|
}
|
|
#endif /*RT_USING_I2C2*/
|
|
|
|
rt_err_t stm32_i2c_register(I2C_TypeDef *I2C, rt_uint32_t bitrate,
|
|
const char * i2c_bus_name)
|
|
{
|
|
struct stm32_i2c_bus *pi2c;
|
|
rt_err_t res;
|
|
|
|
#ifdef RT_USING_I2C1
|
|
if(I2C == I2C1)
|
|
{
|
|
pi2c = &stm32_i2c1;
|
|
RCC_APB2PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
|
|
}
|
|
else
|
|
#endif /*RT_USING_I2C1*/
|
|
#ifdef RT_USING_I2C2
|
|
if(I2C == I2C2)
|
|
{
|
|
pi2c = &stm32_i2c2;
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
|
|
}
|
|
else
|
|
#endif /*RT_USING_I2C2*/
|
|
{
|
|
return RT_ENOSYS;
|
|
}
|
|
if(rt_event_init(&pi2c->ev, i2c_bus_name, RT_IPC_FLAG_FIFO) != RT_EOK)
|
|
{
|
|
return RT_ERROR;
|
|
}
|
|
pi2c->parent.ops = &stm32_i2c_ops;
|
|
if((res = stm_i2c_init(&pi2c->parent, bitrate)) != RT_EOK)
|
|
{
|
|
return res;
|
|
}
|
|
return rt_i2c_bus_device_register(&pi2c->parent, i2c_bus_name);
|
|
}
|
|
#endif /*RT_USING_I2C*/
|