244 lines
8.4 KiB
C
244 lines
8.4 KiB
C
/*
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* File : drv_gpio.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#ifndef __DRV_GPIO_H__
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#define __DRV_GPIO_H__
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/* IO default function */
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#define IO_INPUT (0x00)
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#define IO_OUTPUT (0x01)
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#define IO_DISABLE (0x07)
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#define IO_FUN_1 (0x02)
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#define IO_FUN_2 (0x03)
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#define IO_FUN_3 (0x04)
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#define IO_FUN_4 (0x05)
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#define IO_FUN_5 (0x06)
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/* IO port */
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enum gpio_port
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{
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GPIO_PORT_A = 0,
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GPIO_PORT_B,
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GPIO_PORT_C,
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GPIO_PORT_D,
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GPIO_PORT_E,
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GPIO_PORT_F,
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GPIO_PORT_NUM,
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};
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/* IO pin */
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enum gpio_pin
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{
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GPIO_PIN_0 = 0,
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GPIO_PIN_1,
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GPIO_PIN_2,
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GPIO_PIN_3,
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GPIO_PIN_4,
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GPIO_PIN_5,
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GPIO_PIN_6,
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GPIO_PIN_7,
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GPIO_PIN_8,
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GPIO_PIN_9,
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GPIO_PIN_10,
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GPIO_PIN_11,
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GPIO_PIN_12,
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GPIO_PIN_13,
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GPIO_PIN_14,
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GPIO_PIN_15,
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GPIO_PIN_16,
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GPIO_PIN_17,
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GPIO_PIN_18,
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GPIO_PIN_19,
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GPIO_PIN_20,
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GPIO_PIN_21,
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GPIO_PIN_22,
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GPIO_PIN_23,
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GPIO_PIN_NUM,
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};
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/* Drive level */
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enum gpio_drv_level
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{
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DRV_LEVEL_0 = 0,
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DRV_LEVEL_1,
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DRV_LEVEL_2,
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DRV_LEVEL_3,
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};
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/* Pull mode */
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enum gpio_pull
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{
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PULL_DISABLE = 0,
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PULL_UP,
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PULL_DOWN,
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};
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/* interrupt type */
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enum gpio_irq_type
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{
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POSITIVE = 0,
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NEGATIVE,
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HIGH,
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LOW,
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DOUBLE,
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};
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enum gpio_irq_clock
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{
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GPIO_IRQ_LOSC_32KHZ = 0,
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GPIO_IRQ_HOSC_24MHZ
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};
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enum gpio_direction_type
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{
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DEBOUNCE_PRE_SCALE_1 = 0,
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DEBOUNCE_PRE_SCALE_2,
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DEBOUNCE_PRE_SCALE_4,
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DEBOUNCE_PRE_SCALE_8,
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DEBOUNCE_PRE_SCALE_16,
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DEBOUNCE_PRE_SCALE_32,
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DEBOUNCE_PRE_SCALE_64,
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DEBOUNCE_PRE_SCALE_128,
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};
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struct gpio_irq_def
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{
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void *irq_arg[32];
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void (*irq_cb[32])(void *param);
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};
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#define GPIO_BASE_ADDR (0x01C20800)
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#define GPIOn_CFG_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x00)
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#define GPIOn_DATA_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x10)
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#define GPIOn_DRV_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x14)
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#define GPIOn_PUL_ADDR(n) (GPIO_BASE_ADDR + (n) * 0x24 + 0x1C)
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#define GPIOn_INT_CFG_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x00)
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#define GPIOn_INT_CTRL_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x10)
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#define GPIOn_INT_STA_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x14)
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#define GPIOn_INT_DEB_ADDR(n) (GPIO_BASE_ADDR + 0x200 + (n) * 0x20 + 0x18)
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struct tina_gpio
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{
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volatile rt_uint32_t pa_cfg0; /* 0x00 */
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volatile rt_uint32_t pa_cfg1; /* 0x04 */
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volatile rt_uint32_t pa_cfg2; /* 0x08 */
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volatile rt_uint32_t pa_cfg3; /* 0x0C */
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volatile rt_uint32_t pa_data; /* 0x10 */
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volatile rt_uint32_t pa_drv0; /* 0x14 */
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volatile rt_uint32_t pa_drv1; /* 0x18 */
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volatile rt_uint32_t pa_pul0; /* 0x1C */
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volatile rt_uint32_t pa_pul1; /* 0x20 */
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volatile rt_uint32_t pb_cfg0; /* 0x24 */
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volatile rt_uint32_t pb_cfg1; /* 0x28 */
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volatile rt_uint32_t pb_cfg2; /* 0x2C */
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volatile rt_uint32_t pb_cfg3; /* 0x30 */
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volatile rt_uint32_t pb_data; /* 0x34 */
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volatile rt_uint32_t pb_drv0; /* 0x38 */
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volatile rt_uint32_t pb_drv1; /* 0x3C */
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volatile rt_uint32_t pb_pul0; /* 0x40 */
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volatile rt_uint32_t pb_pul1; /* 0x44 */
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volatile rt_uint32_t pc_cfg0; /* 0x48 */
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volatile rt_uint32_t pc_cfg1; /* 0x4C */
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volatile rt_uint32_t pc_cfg2; /* 0x50 */
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volatile rt_uint32_t pc_cfg3; /* 0x54 */
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volatile rt_uint32_t pc_data; /* 0x58 */
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volatile rt_uint32_t pc_drv0; /* 0x5C */
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volatile rt_uint32_t pc_drv1; /* 0x60 */
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volatile rt_uint32_t pc_pul0; /* 0x64 */
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volatile rt_uint32_t pc_pul1; /* 0x68 */
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volatile rt_uint32_t pd_cfg0; /* 0x6C */
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volatile rt_uint32_t pd_cfg1; /* 0x70 */
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volatile rt_uint32_t pd_cfg2; /* 0x74 */
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volatile rt_uint32_t pd_cfg3; /* 0x78 */
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volatile rt_uint32_t pd_data; /* 0x7C */
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volatile rt_uint32_t pd_drv0; /* 0x80 */
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volatile rt_uint32_t pd_drv1; /* 0x84 */
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volatile rt_uint32_t pd_pul0; /* 0x88 */
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volatile rt_uint32_t pd_pul1; /* 0x8C */
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volatile rt_uint32_t pe_cfg0; /* 0x90 */
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volatile rt_uint32_t pe_cfg1; /* 0x94 */
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volatile rt_uint32_t pe_cfg2; /* 0x98 */
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volatile rt_uint32_t pe_cfg3; /* 0x9C */
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volatile rt_uint32_t pe_data; /* 0xA0 */
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volatile rt_uint32_t pe_drv0; /* 0xA4 */
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volatile rt_uint32_t pe_drv1; /* 0xA8 */
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volatile rt_uint32_t pe_pul0; /* 0xAC */
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volatile rt_uint32_t pe_pul1; /* 0xB0 */
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volatile rt_uint32_t pf_cfg0; /* 0xB4 */
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volatile rt_uint32_t pf_cfg1; /* 0xB8 */
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volatile rt_uint32_t pf_cfg2; /* 0xBC */
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volatile rt_uint32_t pf_cfg3; /* 0xC0 */
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volatile rt_uint32_t pf_data; /* 0xC4 */
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volatile rt_uint32_t pf_drv0; /* 0xC8 */
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volatile rt_uint32_t pf_drv1; /* 0xCC */
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volatile rt_uint32_t pf_pul0; /* 0xD0 */
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volatile rt_uint32_t reserved0[76];
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volatile rt_uint32_t pd_int_cfg0; /* 0x200 */
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volatile rt_uint32_t pd_int_cfg1; /* 0x204 */
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volatile rt_uint32_t pd_int_cfg2; /* 0x208 */
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volatile rt_uint32_t pd_int_cfg3; /* 0x20C */
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volatile rt_uint32_t pd_int_ctrl; /* 0x210 */
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volatile rt_uint32_t pd_int_sta; /* 0x214 */
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volatile rt_uint32_t pd_int_deb; /* 0x218 */
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volatile rt_uint32_t reserved1;
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volatile rt_uint32_t pe_int_cfg0; /* 0x220 */
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volatile rt_uint32_t pe_int_cfg1; /* 0x224 */
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volatile rt_uint32_t pe_int_cfg2; /* 0x228 */
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volatile rt_uint32_t pe_int_cfg3; /* 0x22C */
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volatile rt_uint32_t pe_int_ctrl; /* 0x230 */
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volatile rt_uint32_t pe_int_sta; /* 0x234 */
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volatile rt_uint32_t pe_int_deb; /* 0x238 */
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volatile rt_uint32_t reserved2;
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volatile rt_uint32_t pf_int_cfg0; /* 0x240 */
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volatile rt_uint32_t pf_int_cfg1; /* 0x244 */
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volatile rt_uint32_t pf_int_cfg2; /* 0x248 */
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volatile rt_uint32_t pf_int_cfg3; /* 0x24C */
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volatile rt_uint32_t pf_int_ctrl; /* 0x250 */
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volatile rt_uint32_t pf_int_sta; /* 0x254 */
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volatile rt_uint32_t pf_int_deb; /* 0x258 */
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volatile rt_uint32_t reserved3[26];
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volatile rt_uint32_t sdr_pad_drv; /* 0x2C0*/
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volatile rt_uint32_t sdr_pad_pul; /* 0x2C4 */
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};
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typedef struct tina_gpio *tina_gpio_t;
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#define GPIO ((tina_gpio_t)GPIO_BASE_ADDR)
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int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func);
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int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value);
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int gpio_get_value(enum gpio_port port, enum gpio_pin pin);
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int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull pull);
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int gpio_set_drive_level(enum gpio_port port, enum gpio_pin pin, enum gpio_drv_level level);
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void gpio_direction_input(enum gpio_port port, enum gpio_pin pin);
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void gpio_direction_output(enum gpio_port port, enum gpio_pin pin, int value);
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void gpio_irq_enable(enum gpio_port port, enum gpio_pin pin);
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void gpio_irq_disable(enum gpio_port port, enum gpio_pin pin);
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void gpio_set_irq_type(enum gpio_port port, enum gpio_pin pin, enum gpio_irq_type irq_type);
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void gpio_select_irq_clock(enum gpio_port port, enum gpio_irq_clock clock);
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void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler);
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void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg);
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int rt_hw_gpio_init(void);
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#endif /* __DRV_GPIO_H__ */ |