75 lines
3.9 KiB
C
75 lines
3.9 KiB
C
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : fsmc_sram.c
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* Author : MCD Application Team
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* Version : V2.0.3
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* Date : 09/22/2008
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* Description : This file provides a set of functions needed to drive the
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* IS61WV51216BLL SRAM memory mounted on STM3210E-EVAL board.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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#include "stm32f10x.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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#define Bank1_SRAM3_ADDR ((u32)0x68000000)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/*******************************************************************************
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* Function Name : FSMC_SRAM_Init
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* Description : Configures the FSMC and GPIOs to interface with the SRAM memory.
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* This function must be called before any write/read operation
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* on the SRAM.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void FSMC_SRAM_Init(void)
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{
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FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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FSMC_NORSRAMTimingInitTypeDef p;
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/*-- FSMC Configuration ------------------------------------------------------*/
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p.FSMC_AddressSetupTime = 0;
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p.FSMC_AddressHoldTime = 0;
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p.FSMC_DataSetupTime = 2;
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p.FSMC_BusTurnAroundDuration = 0;
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p.FSMC_CLKDivision = 0;
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p.FSMC_DataLatency = 0;
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p.FSMC_AccessMode = FSMC_AccessMode_A;
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FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
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FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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/* Enable FSMC Bank1_SRAM Bank */
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE);
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}
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/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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