250 lines
8.1 KiB
C
250 lines
8.1 KiB
C
/** @file sys_startup.c
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* @brief Startup Source File
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* @date 29.May.2013
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* @version 03.05.02
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*
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* This file contains:
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* - Include Files
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* - Type Definitions
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* - External Functions
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* - VIM RAM Setup
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* - Startup Routine
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* .
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* which are relevant for the Startup.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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/* Include Files */
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#include "sys_common.h"
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#include "system.h"
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#include "sys_vim.h"
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#include "sys_core.h"
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#include "sys_selftest.h"
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#include "esm.h"
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#include "mibspi.h"
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/* Type Definitions */
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typedef void (*handler_fptr)(const uint8 * in, uint8 * out);
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/* External Functions */
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/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
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/*SAFETYMCUSW 296 S MR:8.6 <REVIEWED> "Startup code(library functions at block scope)" */
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/*SAFETYMCUSW 298 S MR: <REVIEWED> "Startup code(handler pointers)" */
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/*SAFETYMCUSW 299 S MR: <REVIEWED> "Startup code(typedef for handler pointers in library )" */
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/*SAFETYMCUSW 326 S MR:8.2 <REVIEWED> "Startup code(Declaration for main in library)" */
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/*SAFETYMCUSW 60 D MR:8.8 <REVIEWED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
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/*SAFETYMCUSW 94 S MR:11.1 <REVIEWED> "Startup code(handler pointers)" */
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/*SAFETYMCUSW 354 S MR:1.4 <REVIEWED> " Startup code(Extern declaration present in the library)" */
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/*SAFETYMCUSW 218 S MR:20.2 <REVIEWED> "Functions from library" */
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#ifdef __TI_COMPILER_VERSION__
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#pragma WEAK(__TI_Handler_Table_Base)
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#pragma WEAK(__TI_Handler_Table_Limit)
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#pragma WEAK(__TI_CINIT_Base)
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#pragma WEAK(__TI_CINIT_Limit)
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extern uint32 __TI_Handler_Table_Base;
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extern uint32 __TI_Handler_Table_Limit;
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extern uint32 __TI_CINIT_Base;
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extern uint32 __TI_CINIT_Limit;
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extern uint32 __TI_PINIT_Base;
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extern uint32 __TI_PINIT_Limit;
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extern uint32 * __binit__;
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#endif
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extern void main(void);
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/* Startup Routine */
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/** @fn void memoryInit(uint32 ram)
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* @brief Memory Initialization Driver
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*
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* This function is called to perform Memory initialization of selected RAM's.
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*/
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void memoryInit(uint32 ram)
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{
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/* Enable Memory Hardware Initialization */
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systemREG1->MINITGCR = 0xAU;
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/* Enable Memory Hardware Initialization for selected RAM's */
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systemREG1->MSINENA = ram;
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/* Wait until Memory Hardware Initialization complete */
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while((systemREG1->MSTCGSTAT & 0x00000100U) != 0x00000100U)
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{
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}/* Wait */
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/* Disable Memory Hardware Initialization */
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systemREG1->MINITGCR = 0x5U;
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}
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void _c_int00(void)
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{
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/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
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*
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* Errata Description:
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* The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
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* Workaround:
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* Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
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if (DEVICE_ID_REV == 0x802AAD05U)
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{
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_esmCcmErrorsClear_();
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}
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_errata_CORTEXR4_66_();
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_errata_CORTEXR4_57_();
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/* Reset handler: the following instructions read from the system exception status register
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* to identify the cause of the CPU reset. */
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/* check for power-on reset condition */
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if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
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{
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/* clear all reset status flags */
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SYS_EXCEPTION = 0xFFFFU;
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/* continue with normal start-up sequence */
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}
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else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
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{
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/* Reset caused due to oscillator failure.
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Add user code here to handle oscillator failure */
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}
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else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
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{
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/* Reset caused due
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* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
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* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
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*/
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/* Check the WatchDog Status register */
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if(WATCHDOG_STATUS != 0U)
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{
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/* Add user code here to handle watchdog violation. */
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/* Clear the Watchdog reset flag in Exception Status register */
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SYS_EXCEPTION = WATCHDOG_RESET;
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}
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else
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{
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/* Clear the ICEPICK reset flag in Exception Status register */
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SYS_EXCEPTION = ICEPICK_RESET;
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}
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}
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else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
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{
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/* Reset caused due to CPU reset.
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CPU reset can be caused by CPU self-test completion, or
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by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
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/* clear all reset status flags */
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SYS_EXCEPTION = CPU_RESET;
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}
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else if ((SYS_EXCEPTION & SW_RESET) != 0U)
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{
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/* Reset caused due to software reset.
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Add user code to handle software reset. */
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}
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else
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{
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/* Reset caused by nRST being driven low externally.
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Add user code to handle external reset. */
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}
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/* Initialize System - Clock, Flash settings with Efuse self check */
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systemInit();
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/* Initialize CPU RAM.
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* This function uses the system module's hardware for auto-initialization of memories and their
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* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
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* Hence the value 0x1 passed to the function.
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* This function will initialize the entire CPU RAM and the corresponding ECC locations.
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*/
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memoryInit(0x1U);
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_coreEnableRamEcc_();
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/* Release the MibSPI1 modules from local reset.
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* This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
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*/
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mibspiREG1->GCR0 = 0x1U;
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/* Release the MibSPI3 modules from local reset.
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* This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
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*/
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mibspiREG3->GCR0 = 0x1U;
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/* Release the MibSPI5 modules from local reset.
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* This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
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*/
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mibspiREG5->GCR0 = 0x1U;
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/* Initialize all on-chip SRAMs except for MibSPIx RAMs The MibSPIx modules
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* have their own auto-initialization mechanism which is triggered as soon
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* as the modules are brought out of local reset. */
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/* The system module auto-init will hang on the MibSPI RAM if the module is
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* still in local reset. */
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/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories
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* and their channel numbers. Memory Initialization is perfomed only on
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* the user selected memories in HALCoGen's GUI SAFETY INIT tab. */
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memoryInit((1U << 1U) | (1U << 2U) | (1U << 5U) | (1U << 6U)
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| (1U << 10U) | (1U << 8U) | (1U << 14U) | (1U << 3U)
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| (1U << 4U) | (1U << 15U) | (1U << 16U) | (0U << 13U) );
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while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
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{
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}/* Wait */
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/* wait for MibSPI1 RAM to complete initialization */
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while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
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{
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}/* Wait */
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/* wait for MibSPI3 RAM to complete initialization */
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while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
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{
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}/* Wait */
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/* wait for MibSPI5 RAM to complete initialization */
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/* Initialize VIM table */
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vimInit();
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#ifdef __GNUC__
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data_init();
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#elif defined(__TI_COMPILER_VERSION__)
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/* initialize copy table */
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if ((uint32 *)&__binit__ != (uint32 *)0xFFFFFFFFU)
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{
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extern void copy_in(void * binit);
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copy_in((void *)&__binit__);
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}
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/* initialize the C global variables */
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if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)
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{
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uint8 **tablePtr = (uint8 **)&__TI_CINIT_Base;
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uint8 **tableLimit = (uint8 **)&__TI_CINIT_Limit;
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while (tablePtr < tableLimit)
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{
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uint8 * loadAdr = *tablePtr++;
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uint8 * runAdr = *tablePtr++;
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uint8 idx = *loadAdr++;
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handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];
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(*handler)((const uint8 *)loadAdr, runAdr);
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}
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}
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/* initialize constructors */
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if (__TI_PINIT_Base < __TI_PINIT_Limit)
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{
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void (**p0)(void) = (void *)__TI_PINIT_Base;
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while ((uint32)p0 < __TI_PINIT_Limit)
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{
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void (*p)(void) = *p0++;
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p();
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}
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}
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#endif
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/* call the application */
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main();
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}
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