432 lines
16 KiB
C
432 lines
16 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_RCM_H_
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#define _FSL_RCM_H_
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#include "fsl_common.h"
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/*! @addtogroup rcm */
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/*! @{*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief RCM driver version 2.0.1. */
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#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
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/*@}*/
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/*!
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* @brief System Reset Source Name definitions
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*/
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typedef enum _rcm_reset_source
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{
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#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
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/* RCM register bit width is 32. */
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#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
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kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
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#endif
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kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */
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#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
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kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */
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#endif /* FSL_FEATURE_RCM_HAS_LOC */
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#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
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kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */
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#endif /* FSL_FEATURE_RCM_HAS_LOL */
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kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */
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kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */
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kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */
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#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
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kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */
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#endif /* FSL_FEATURE_RCM_HAS_JTAG */
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kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */
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kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */
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#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
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kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */
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#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
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#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
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kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */
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#endif /* FSL_FEATURE_RCM_HAS_EZPORT */
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kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */
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#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
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/* RCM register bit width is 8. */
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#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
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kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
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#endif
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kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */
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#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
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kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */
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#endif /* FSL_FEATURE_RCM_HAS_LOC */
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#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
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kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */
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#endif /* FSL_FEATURE_RCM_HAS_LOL */
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kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */
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kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */
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kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */
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#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
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kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */
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#endif /* FSL_FEATURE_RCM_HAS_JTAG */
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kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */
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kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */
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#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
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kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */
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#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
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#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
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kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */
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#endif /* FSL_FEATURE_RCM_HAS_EZPORT */
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kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */
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#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
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kRCM_SourceAll = 0xffffffffU,
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} rcm_reset_source_t;
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/*!
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* @brief Reset pin filter select in Run and Wait modes.
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*/
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typedef enum _rcm_run_wait_filter_mode
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{
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kRCM_FilterDisable = 0U, /*!< All filtering disabled */
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kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */
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kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */
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} rcm_run_wait_filter_mode_t;
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#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
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/*!
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* @brief Boot from ROM configuration.
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*/
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typedef enum _rcm_boot_rom_config
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{
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kRCM_BootFlash = 0U, /*!< Boot from flash */
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kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */
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kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */
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kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */
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} rcm_boot_rom_config_t;
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#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
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#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
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/*!
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* @brief Maximum delay time from interrupt asserts to system reset.
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*/
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typedef enum _rcm_reset_delay
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{
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kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */
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kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */
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kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */
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kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */
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} rcm_reset_delay_t;
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/*!
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* @brief System reset interrupt enable bit definitions.
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*/
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typedef enum _rcm_interrupt_enable
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{
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kRCM_IntNone = 0U, /*!< No interrupt enabled. */
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kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */
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kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */
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kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */
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kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */
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kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */
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kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */
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kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */
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kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */
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#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
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kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */
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#endif
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kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */
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RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK |
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RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK
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#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
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RCM_SRIE_CORE1_MASK
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#endif
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} rcm_interrupt_enable_t;
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#endif /* FSL_FEATURE_RCM_HAS_SRIE */
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#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
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/*!
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* @brief IP version ID definition.
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*/
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typedef struct _rcm_version_id
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{
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uint16_t feature; /*!< Feature Specification Number. */
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uint8_t minor; /*!< Minor version number. */
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uint8_t major; /*!< Major version number. */
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} rcm_version_id_t;
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#endif
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/*!
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* @brief Reset pin filter configuration.
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*/
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typedef struct _rcm_reset_pin_filter_config
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{
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bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */
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rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */
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uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */
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} rcm_reset_pin_filter_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*! @name Reset Control Module APIs*/
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/*@{*/
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#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
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/*!
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* @brief Gets the RCM version ID.
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*
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* This function gets the RCM version ID including the major version number,
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* the minor version number, and the feature specification number.
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*
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* @param base RCM peripheral base address.
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* @param versionId Pointer to the version ID structure.
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*/
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static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
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{
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*((uint32_t *)versionId) = base->VERID;
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}
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#endif
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#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM)
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/*!
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* @brief Gets the reset source implemented status.
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*
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* This function gets the RCM parameter that indicates whether the corresponding reset source is implemented.
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* Use source masks defined in the rcm_reset_source_t to get the desired source status.
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*
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* This is an example.
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@code
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uint32_t status;
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// To test whether the MCU is reset using Watchdog.
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status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
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@endcode
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*
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* @param base RCM peripheral base address.
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* @return All reset source implemented status bit map.
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*/
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static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base)
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{
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return base->PARAM;
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}
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#endif /* FSL_FEATURE_RCM_HAS_PARAM */
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/*!
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* @brief Gets the reset source status which caused a previous reset.
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*
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* This function gets the current reset source status. Use source masks
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* defined in the rcm_reset_source_t to get the desired source status.
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*
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* This is an example.
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@code
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uint32_t resetStatus;
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// To get all reset source statuses.
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resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll;
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// To test whether the MCU is reset using Watchdog.
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resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog;
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// To test multiple reset sources.
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resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
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@endcode
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*
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* @param base RCM peripheral base address.
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* @return All reset source status bit map.
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*/
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static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base)
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{
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#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
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return base->SRS;
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#else
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return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U));
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#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
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}
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#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS)
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/*!
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* @brief Gets the sticky reset source status.
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*
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* This function gets the current reset source status that has not been cleared
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* by software for a specific source.
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*
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* This is an example.
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@code
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uint32_t resetStatus;
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// To get all reset source statuses.
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resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll;
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// To test whether the MCU is reset using Watchdog.
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resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog;
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// To test multiple reset sources.
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resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
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@endcode
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*
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* @param base RCM peripheral base address.
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* @return All reset source status bit map.
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*/
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static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base)
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{
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#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
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return base->SSRS;
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#else
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return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U));
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#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
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}
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/*!
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* @brief Clears the sticky reset source status.
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*
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* This function clears the sticky system reset flags indicated by source masks.
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*
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* This is an example.
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@code
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// Clears multiple reset sources.
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RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin);
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@endcode
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*
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* @param base RCM peripheral base address.
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* @param sourceMasks reset source status bit map
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*/
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static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks)
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{
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#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
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base->SSRS = sourceMasks;
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#else
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base->SSRS0 = (sourceMasks & 0xffU);
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base->SSRS1 = ((sourceMasks >> 8U) & 0xffU);
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#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
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}
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#endif /* FSL_FEATURE_RCM_HAS_SSRS */
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/*!
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* @brief Configures the reset pin filter.
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*
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* This function sets the reset pin filter including the filter source, filter
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* width, and so on.
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*
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* @param base RCM peripheral base address.
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* @param config Pointer to the configuration structure.
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*/
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void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config);
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#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS)
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/*!
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* @brief Gets the EZP_MS_B pin assert status.
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*
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* This function gets the easy port mode status (EZP_MS_B) pin assert status.
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*
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* @param base RCM peripheral base address.
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* @return status true - asserted, false - reasserted
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*/
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static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base)
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{
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return (bool)(base->MR & RCM_MR_EZP_MS_MASK);
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}
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#endif /* FSL_FEATURE_RCM_HAS_EZPMS */
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#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
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/*!
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* @brief Gets the ROM boot source.
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*
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* This function gets the ROM boot source during the last chip reset.
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*
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* @param base RCM peripheral base address.
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* @return The ROM boot source.
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*/
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static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base)
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{
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return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT);
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}
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/*!
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* @brief Clears the ROM boot source flag.
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*
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* This function clears the ROM boot source flag.
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*
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* @param base Register base address of RCM
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*/
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static inline void RCM_ClearBootRomSource(RCM_Type *base)
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{
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base->MR |= RCM_MR_BOOTROM_MASK;
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}
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/*!
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* @brief Forces the boot from ROM.
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*
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* This function forces booting from ROM during all subsequent system resets.
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*
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* @param base RCM peripheral base address.
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* @param config Boot configuration.
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*/
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void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config);
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#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
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#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
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/*!
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* @brief Sets the system reset interrupt configuration.
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*
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* For a graceful shut down, the RCM supports delaying the assertion of the system
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* reset for a period of time when the reset interrupt is generated. This function
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* can be used to enable the interrupt and the delay period. The interrupts
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* are passed in as bit mask. See rcm_int_t for details. For example, to
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* delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs,
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* configure as follows:
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* RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo);
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*
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* @param base RCM peripheral base address.
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* @param intMask Bit mask of the system reset interrupts to enable. See
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* rcm_interrupt_enable_t for details.
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* @param Delay Bit mask of the system reset interrupts to enable.
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*/
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static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay)
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{
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base->SRIE = (intMask | delay);
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}
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#endif /* FSL_FEATURE_RCM_HAS_SRIE */
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/*@}*/
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*! @}*/
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#endif /* _FSL_RCM_H_ */
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