432 lines
16 KiB
C
432 lines
16 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_PORT_H_
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#define _FSL_PORT_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup port
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! Version 2.0.2. */
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#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
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/*@}*/
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#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
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/*! @brief Internal resistor pull feature selection */
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enum _port_pull
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{
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kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
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kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
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kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
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};
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#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
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#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
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/*! @brief Slew rate selection */
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enum _port_slew_rate
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{
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kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
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kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
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};
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#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
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#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
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/*! @brief Open Drain feature enable/disable */
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enum _port_open_drain_enable
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{
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kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
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kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
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};
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#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
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#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
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/*! @brief Passive filter feature enable/disable */
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enum _port_passive_filter_enable
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{
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kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
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kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
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};
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#endif
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#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
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/*! @brief Configures the drive strength. */
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enum _port_drive_strength
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{
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kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
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kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
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};
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#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
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#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
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/*! @brief Unlock/lock the pin control register field[15:0] */
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enum _port_lock_register
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{
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kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
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kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
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};
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#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
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#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
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/*! @brief Pin mux selection */
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typedef enum _port_mux
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{
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kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
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kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
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kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
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kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
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kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
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kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
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kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
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kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
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kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
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kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
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kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
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kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
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kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
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kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
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kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
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kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
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} port_mux_t;
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#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
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/*! @brief Configures the interrupt generation condition. */
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typedef enum _port_interrupt
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{
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kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
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#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
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kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
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kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
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kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
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#endif
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#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
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kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
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kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
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kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
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#endif
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kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
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kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
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kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
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kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
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kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
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#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
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kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
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kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
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#endif
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} port_interrupt_t;
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#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
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/*! @brief Digital filter clock source selection */
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typedef enum _port_digital_filter_clock_source
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{
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kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
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kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
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} port_digital_filter_clock_source_t;
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/*! @brief PORT digital filter feature configuration definition */
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typedef struct _port_digital_filter_config
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{
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uint32_t digitalFilterWidth; /*!< Set digital filter width */
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port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
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} port_digital_filter_config_t;
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#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
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#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
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/*! @brief PORT pin configuration structure */
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typedef struct _port_pin_config
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{
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#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
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uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
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#else
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uint16_t : 2;
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#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
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#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
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uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
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#else
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uint16_t : 1;
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#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
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uint16_t : 1;
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#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
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uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
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#else
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uint16_t : 1;
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#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
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#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
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uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
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#else
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uint16_t : 1;
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#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
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#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
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uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
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#else
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uint16_t : 1;
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#endif
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uint16_t : 1;
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#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
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uint16_t mux : 3; /*!< Pin mux Configure */
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#else
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uint16_t : 3;
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#endif
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uint16_t : 4;
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#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
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uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
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#else
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uint16_t : 1;
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#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
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} port_pin_config_t;
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#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
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/*! @name Configuration */
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/*@{*/
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/*!
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* @brief Sets the port PCR register.
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*
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* This is an example to define an input pin or output pin PCR configuration.
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* @code
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* // Define a digital input pin PCR configuration
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* port_pin_config_t config = {
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* kPORT_PullUp,
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* kPORT_FastSlewRate,
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* kPORT_PassiveFilterDisable,
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* kPORT_OpenDrainDisable,
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* kPORT_LowDriveStrength,
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* kPORT_MuxAsGpio,
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* kPORT_UnLockRegister,
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* };
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* @endcode
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*
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* @param base PORT peripheral base pointer.
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* @param pin PORT pin number.
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* @param config PORT PCR register configuration structure.
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*/
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static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
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{
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assert(config);
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uint32_t addr = (uint32_t)&base->PCR[pin];
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*(volatile uint16_t *)(addr) = *((const uint16_t *)config);
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}
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/*!
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* @brief Sets the port PCR register for multiple pins.
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*
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* This is an example to define input pins or output pins PCR configuration.
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* @code
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* // Define a digital input pin PCR configuration
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* port_pin_config_t config = {
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* kPORT_PullUp ,
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* kPORT_PullEnable,
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* kPORT_FastSlewRate,
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* kPORT_PassiveFilterDisable,
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* kPORT_OpenDrainDisable,
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* kPORT_LowDriveStrength,
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* kPORT_MuxAsGpio,
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* kPORT_UnlockRegister,
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* };
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* @endcode
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*
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* @param base PORT peripheral base pointer.
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* @param mask PORT pin number macro.
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* @param config PORT PCR register configuration structure.
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*/
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static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
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{
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assert(config);
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uint16_t pcrl = *((const uint16_t *)config);
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if (mask & 0xffffU)
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{
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base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
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}
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if (mask >> 16)
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{
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base->GPCHR = (mask & 0xffff0000U) | pcrl;
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}
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}
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/*!
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* @brief Configures the pin muxing.
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*
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* @param base PORT peripheral base pointer.
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* @param pin PORT pin number.
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* @param mux pin muxing slot selection.
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* - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
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* - #kPORT_MuxAsGpio : Set as GPIO.
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* - #kPORT_MuxAlt2 : chip-specific.
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* - #kPORT_MuxAlt3 : chip-specific.
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* - #kPORT_MuxAlt4 : chip-specific.
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* - #kPORT_MuxAlt5 : chip-specific.
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* - #kPORT_MuxAlt6 : chip-specific.
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* - #kPORT_MuxAlt7 : chip-specific.
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* @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
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* the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
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* reset to zero : kPORT_PinDisabledOrAnalog).
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* This function is recommended to use to reset the pin mux
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*
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*/
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static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
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{
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base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
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}
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#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
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#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
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/*!
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* @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
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*
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* @param base PORT peripheral base pointer.
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* @param mask PORT pin number macro.
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*/
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static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
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{
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if (enable == true)
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{
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base->DFER |= mask;
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}
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else
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{
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base->DFER &= ~mask;
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}
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}
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/*!
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* @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
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*
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* @param base PORT peripheral base pointer.
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* @param config PORT digital filter configuration structure.
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*/
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static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
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{
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assert(config);
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base->DFCR = PORT_DFCR_CS(config->clockSource);
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base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
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}
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#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
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/*@}*/
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/*! @name Interrupt */
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/*@{*/
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/*!
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* @brief Configures the port pin interrupt/DMA request.
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*
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* @param base PORT peripheral base pointer.
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* @param pin PORT pin number.
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* @param config PORT pin interrupt configuration.
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* - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
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* - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
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* - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
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* - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
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* - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
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* - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
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* - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
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* - #kPORT_InterruptLogicZero : Interrupt when logic zero.
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* - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
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* - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
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* - #kPORT_InterruptEitherEdge : Interrupt on either edge.
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* - #kPORT_InterruptLogicOne : Interrupt when logic one.
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* - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
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* - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
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*/
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static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
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{
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base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
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}
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/*!
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* @brief Reads the whole port status flag.
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*
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* If a pin is configured to generate the DMA request, the corresponding flag
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* is cleared automatically at the completion of the requested DMA transfer.
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* Otherwise, the flag remains set until a logic one is written to that flag.
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* If configured for a level sensitive interrupt that remains asserted, the flag
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* is set again immediately.
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*
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* @param base PORT peripheral base pointer.
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* @return Current port interrupt status flags, for example, 0x00010001 means the
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* pin 0 and 16 have the interrupt.
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*/
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static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
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{
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return base->ISFR;
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}
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/*!
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* @brief Clears the multiple pin interrupt status flag.
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*
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* @param base PORT peripheral base pointer.
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* @param mask PORT pin number macro.
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*/
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static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
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{
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base->ISFR = mask;
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}
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/*@}*/
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_PORT_H_ */
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