1408 lines
44 KiB
C
1408 lines
44 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexcan.h"
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/*******************************************************************************
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* Definitons
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******************************************************************************/
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#define FLEXCAN_TIME_QUANTA_NUM (10)
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/*! @brief FlexCAN Internal State. */
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enum _flexcan_state
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{
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kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/
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kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/
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kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/
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kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/
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kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/
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kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/
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};
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/*! @brief FlexCAN message buffer CODE for Rx buffers. */
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enum _flexcan_mb_code_rx
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{
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kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/
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kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/
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kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/
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kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/
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kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/
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/*! The CPU must not access the MB.*/
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kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */
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/*! and transmit a Response Frame in return.*/
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kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/
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};
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/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */
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enum _flexcan_mb_code_tx
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{
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kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/
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kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/
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kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */
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/*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/
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kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */
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/*! an incoming Remote Request Frame.*/
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kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/
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};
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/* Typedef for interrupt handler. */
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typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the FlexCAN instance from peripheral base address.
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*
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* @param base FlexCAN peripheral base address.
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* @return FlexCAN instance.
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*/
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uint32_t FLEXCAN_GetInstance(CAN_Type *base);
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/*!
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* @brief Enter FlexCAN Freeze Mode.
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*
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* This function makes the FlexCAN work under Freeze Mode.
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*
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* @param base FlexCAN peripheral base address.
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*/
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static void FLEXCAN_EnterFreezeMode(CAN_Type *base);
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/*!
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* @brief Exit FlexCAN Freeze Mode.
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*
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* This function makes the FlexCAN leave Freeze Mode.
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*
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* @param base FlexCAN peripheral base address.
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*/
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static void FLEXCAN_ExitFreezeMode(CAN_Type *base);
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#if !defined(NDEBUG)
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/*!
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* @brief Check if Message Buffer is occupied by Rx FIFO.
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*
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* This function check if Message Buffer is occupied by Rx FIFO.
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*
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* @param base FlexCAN peripheral base address.
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* @param mbIdx The FlexCAN Message Buffer index.
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*/
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static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx);
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#endif
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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/*!
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* @brief Get the first valid Message buffer ID of give FlexCAN instance.
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*
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* This function is a helper function for Errata 5641 workaround.
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*
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* @param base FlexCAN peripheral base address.
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* @return The first valid Message Buffer Number.
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*/
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static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base);
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#endif
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/*!
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* @brief Check if Message Buffer interrupt is enabled.
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*
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* This function check if Message Buffer interrupt is enabled.
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*
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* @param base FlexCAN peripheral base address.
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* @param mbIdx The FlexCAN Message Buffer index.
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*/
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static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx);
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/*!
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* @brief Reset the FlexCAN Instance.
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*
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* Restores the FlexCAN module to reset state, notice that this function
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* will set all the registers to reset state so the FlexCAN module can not work
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* after calling this API.
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*
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* @param base FlexCAN peripheral base address.
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*/
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static void FLEXCAN_Reset(CAN_Type *base);
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/*!
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* @brief Set Baud Rate of FlexCAN.
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*
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* This function set the baud rate of FlexCAN.
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*
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* @param base FlexCAN peripheral base address.
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* @param sourceClock_Hz Source Clock in Hz.
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* @param baudRate_Bps Baud Rate in Bps.
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*/
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static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of FlexCAN peripheral base address. */
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static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
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/* Array of FlexCAN IRQ number. */
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static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS;
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static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS;
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static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS;
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static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS;
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static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS;
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static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS;
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/* Array of FlexCAN handle. */
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static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)];
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Array of FlexCAN clock name. */
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static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS;
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#if defined(FLEXCAN_PERIPH_CLOCKS)
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/* Array of FlexCAN serial clock name. */
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static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS;
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#endif /* FLEXCAN_PERIPH_CLOCKS */
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* FlexCAN ISR for transactional APIs. */
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static flexcan_isr_t s_flexcanIsr;
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/*******************************************************************************
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* Code
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******************************************************************************/
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uint32_t FLEXCAN_GetInstance(CAN_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++)
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{
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if (s_flexcanBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_flexcanBases));
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return instance;
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}
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static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
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{
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/* Set Freeze, Halt bits. */
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base->MCR |= CAN_MCR_HALT_MASK;
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/* Wait until the FlexCAN Module enter freeze mode. */
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while (!(base->MCR & CAN_MCR_FRZACK_MASK))
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{
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}
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}
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static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
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{
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/* Clear Freeze, Halt bits. */
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base->MCR &= ~CAN_MCR_HALT_MASK;
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/* Wait until the FlexCAN Module exit freeze mode. */
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while (base->MCR & CAN_MCR_FRZACK_MASK)
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{
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}
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}
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#if !defined(NDEBUG)
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static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx)
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{
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uint8_t lastOccupiedMb;
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/* Is Rx FIFO enabled? */
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if (base->MCR & CAN_MCR_RFEN_MASK)
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{
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/* Get RFFN value. */
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lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
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/* Calculate the number of last Message Buffer occupied by Rx FIFO. */
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lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5;
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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if (mbIdx <= (lastOccupiedMb + 1))
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#else
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if (mbIdx <= lastOccupiedMb)
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#endif
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{
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return true;
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}
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else
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{
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return false;
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}
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}
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else
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{
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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if (0 == mbIdx)
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{
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return true;
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}
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else
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{
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return false;
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}
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#else
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return false;
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#endif
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}
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}
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#endif
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
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static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base)
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{
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uint32_t firstValidMbNum;
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if (base->MCR & CAN_MCR_RFEN_MASK)
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{
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firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
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firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6;
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}
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else
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{
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firstValidMbNum = 0;
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}
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return firstValidMbNum;
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}
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#endif
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static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx)
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{
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/* Assertion. */
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assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base));
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#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
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if (mbIdx < 32)
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{
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#endif
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if (base->IMASK1 & ((uint32_t)(1 << mbIdx)))
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{
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return true;
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}
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else
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{
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return false;
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}
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#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
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}
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else
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{
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if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32))))
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{
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return true;
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}
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else
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{
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return false;
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}
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}
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#endif
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}
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static void FLEXCAN_Reset(CAN_Type *base)
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{
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/* The module must should be first exit from low power
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* mode, and then soft reset can be applied.
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*/
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assert(!(base->MCR & CAN_MCR_MDIS_MASK));
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uint8_t i;
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#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0)
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/* De-assert DOZE Enable Bit. */
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base->MCR &= ~CAN_MCR_DOZE_MASK;
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#endif
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/* Wait until FlexCAN exit from any Low Power Mode. */
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while (base->MCR & CAN_MCR_LPMACK_MASK)
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{
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}
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/* Assert Soft Reset Signal. */
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base->MCR |= CAN_MCR_SOFTRST_MASK;
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/* Wait until FlexCAN reset completes. */
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while (base->MCR & CAN_MCR_SOFTRST_MASK)
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{
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}
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/* Reset MCR rigister. */
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#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER)
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base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK |
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CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
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#else
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base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1);
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#endif
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/* Reset CTRL1 and CTRL2 rigister. */
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base->CTRL1 = CAN_CTRL1_SMP_MASK;
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base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK;
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/* Clean all individual Rx Mask of Message Buffers. */
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for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++)
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{
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base->RXIMR[i] = 0x3FFFFFFF;
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}
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/* Clean Global Mask of Message Buffers. */
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base->RXMGMASK = 0x3FFFFFFF;
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/* Clean Global Mask of Message Buffer 14. */
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base->RX14MASK = 0x3FFFFFFF;
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/* Clean Global Mask of Message Buffer 15. */
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base->RX15MASK = 0x3FFFFFFF;
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/* Clean Global Mask of Rx FIFO. */
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base->RXFGMASK = 0x3FFFFFFF;
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/* Clean all Message Buffer CS fields. */
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for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++)
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{
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base->MB[i].CS = 0x0;
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}
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}
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static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps)
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{
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flexcan_timing_config_t timingConfig;
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uint32_t priDiv = baudRate_Bps * FLEXCAN_TIME_QUANTA_NUM;
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/* Assertion: Desired baud rate is too high. */
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assert(baudRate_Bps <= 1000000U);
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/* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */
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assert(priDiv <= sourceClock_Hz);
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if (0 == priDiv)
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{
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priDiv = 1;
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}
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priDiv = (sourceClock_Hz / priDiv) - 1;
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/* Desired baud rate is too low. */
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if (priDiv > 0xFF)
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{
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priDiv = 0xFF;
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}
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/* FlexCAN timing setting formula:
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* FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1);
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*/
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timingConfig.preDivider = priDiv;
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timingConfig.phaseSeg1 = 3;
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timingConfig.phaseSeg2 = 2;
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timingConfig.propSeg = 1;
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timingConfig.rJumpwidth = 1;
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/* Update actual timing characteristic. */
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FLEXCAN_SetTimingConfig(base, &timingConfig);
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}
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void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz)
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{
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uint32_t mcrTemp;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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uint32_t instance;
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#endif
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/* Assertion. */
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assert(config);
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assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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instance = FLEXCAN_GetInstance(base);
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/* Enable FlexCAN clock. */
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CLOCK_EnableClock(s_flexcanClock[instance]);
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#if defined(FLEXCAN_PERIPH_CLOCKS)
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/* Enable FlexCAN serial clock. */
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CLOCK_EnableClock(s_flexcanPeriphClock[instance]);
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#endif /* FLEXCAN_PERIPH_CLOCKS */
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
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/* Disable FlexCAN Module. */
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FLEXCAN_Enable(base, false);
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/* Protocol-Engine clock source selection, This bit must be set
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* when FlexCAN Module in Disable Mode.
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*/
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base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK :
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base->CTRL1 | CAN_CTRL1_CLKSRC_MASK;
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#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
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/* Enable FlexCAN Module for configuartion. */
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FLEXCAN_Enable(base, true);
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/* Reset to known status. */
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FLEXCAN_Reset(base);
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/* Save current MCR value and enable to enter Freeze mode(enabled by default). */
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mcrTemp = base->MCR;
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/* Set the maximum number of Message Buffers */
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mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1);
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/* Enable Loop Back Mode? */
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base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK;
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/* Enable Self Wake Up Mode? */
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mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK;
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|
|
|
/* Enable Individual Rx Masking? */
|
|
mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK;
|
|
|
|
#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
|
|
/* Enable Doze Mode? */
|
|
mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK;
|
|
#endif
|
|
|
|
/* Save MCR Configuation. */
|
|
base->MCR = mcrTemp;
|
|
|
|
/* Baud Rate Configuration.*/
|
|
FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate);
|
|
}
|
|
|
|
void FLEXCAN_Deinit(CAN_Type *base)
|
|
{
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
uint32_t instance;
|
|
#endif
|
|
/* Reset all Register Contents. */
|
|
FLEXCAN_Reset(base);
|
|
|
|
/* Disable FlexCAN module. */
|
|
FLEXCAN_Enable(base, false);
|
|
|
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
|
instance = FLEXCAN_GetInstance(base);
|
|
#if defined(FLEXCAN_PERIPH_CLOCKS)
|
|
/* Disable FlexCAN serial clock. */
|
|
CLOCK_DisableClock(s_flexcanPeriphClock[instance]);
|
|
#endif /* FLEXCAN_PERIPH_CLOCKS */
|
|
/* Disable FlexCAN clock. */
|
|
CLOCK_DisableClock(s_flexcanClock[instance]);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
}
|
|
|
|
void FLEXCAN_GetDefaultConfig(flexcan_config_t *config)
|
|
{
|
|
/* Assertion. */
|
|
assert(config);
|
|
|
|
/* Initialize FlexCAN Module config struct with default value. */
|
|
#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
|
|
config->clkSrc = kFLEXCAN_ClkSrcOsc;
|
|
#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
|
|
config->baudRate = 125000U;
|
|
config->maxMbNum = 16;
|
|
config->enableLoopBack = false;
|
|
config->enableSelfWakeup = false;
|
|
config->enableIndividMask = false;
|
|
#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
|
|
config->enableDoze = false;
|
|
#endif
|
|
}
|
|
|
|
void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config)
|
|
{
|
|
/* Assertion. */
|
|
assert(config);
|
|
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
/* Cleaning previous Timing Setting. */
|
|
base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK |
|
|
CAN_CTRL1_PROPSEG_MASK);
|
|
|
|
/* Updating Timing Setting according to configuration structure. */
|
|
base->CTRL1 |=
|
|
(CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) |
|
|
CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg));
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
|
|
void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask)
|
|
{
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
/* Setting Rx Message Buffer Global Mask value. */
|
|
base->RXMGMASK = mask;
|
|
base->RX14MASK = mask;
|
|
base->RX15MASK = mask;
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
|
|
void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask)
|
|
{
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
/* Setting Rx FIFO Global Mask value. */
|
|
base->RXFGMASK = mask;
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
|
|
void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask)
|
|
{
|
|
assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
/* Setting Rx Individual Mask value. */
|
|
base->RXIMR[maskIdx] = mask;
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
|
|
void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
|
|
{
|
|
/* Assertion. */
|
|
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
|
|
|
/* Inactivate Message Buffer. */
|
|
if (enable)
|
|
{
|
|
base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
|
}
|
|
else
|
|
{
|
|
base->MB[mbIdx].CS = 0;
|
|
}
|
|
|
|
/* Clean Message Buffer content. */
|
|
base->MB[mbIdx].ID = 0x0;
|
|
base->MB[mbIdx].WORD0 = 0x0;
|
|
base->MB[mbIdx].WORD1 = 0x0;
|
|
}
|
|
|
|
void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable)
|
|
{
|
|
/* Assertion. */
|
|
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(((config) || (false == enable)));
|
|
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
|
|
|
uint32_t cs_temp = 0;
|
|
|
|
/* Inactivate Message Buffer. */
|
|
base->MB[mbIdx].CS = 0;
|
|
|
|
/* Clean Message Buffer content. */
|
|
base->MB[mbIdx].ID = 0x0;
|
|
base->MB[mbIdx].WORD0 = 0x0;
|
|
base->MB[mbIdx].WORD1 = 0x0;
|
|
|
|
if (enable)
|
|
{
|
|
/* Setup Message Buffer ID. */
|
|
base->MB[mbIdx].ID = config->id;
|
|
|
|
/* Setup Message Buffer format. */
|
|
if (kFLEXCAN_FrameFormatExtend == config->format)
|
|
{
|
|
cs_temp |= CAN_CS_IDE_MASK;
|
|
}
|
|
|
|
/* Setup Message Buffer type. */
|
|
if (kFLEXCAN_FrameTypeRemote == config->type)
|
|
{
|
|
cs_temp |= CAN_CS_RTR_MASK;
|
|
}
|
|
|
|
/* Activate Rx Message Buffer. */
|
|
cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty);
|
|
base->MB[mbIdx].CS = cs_temp;
|
|
}
|
|
}
|
|
|
|
void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable)
|
|
{
|
|
/* Assertion. */
|
|
assert((config) || (false == enable));
|
|
|
|
volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS);
|
|
uint8_t setup_mb, i, rffn = 0;
|
|
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
if (enable)
|
|
{
|
|
assert(config->idFilterNum <= 128);
|
|
|
|
/* Get the setup_mb value. */
|
|
setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT;
|
|
setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ?
|
|
setup_mb :
|
|
FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base);
|
|
|
|
/* Determine RFFN value. */
|
|
for (i = 0; i <= 0xF; i++)
|
|
{
|
|
if ((8 * (i + 1)) >= config->idFilterNum)
|
|
{
|
|
rffn = i;
|
|
assert(((setup_mb - 8) - (2 * rffn)) > 0);
|
|
|
|
base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT;
|
|
}
|
|
|
|
/* Clean ID filter table occuyied Message Buffer Region. */
|
|
rffn = (rffn + 1) * 8;
|
|
for (i = 0; i < rffn; i++)
|
|
{
|
|
idFilterRegion[i] = 0x0;
|
|
}
|
|
|
|
if (enable)
|
|
{
|
|
/* Disable unused Rx FIFO Filter. */
|
|
for (i = config->idFilterNum; i < rffn; i++)
|
|
{
|
|
idFilterRegion[i] = 0xFFFFFFFFU;
|
|
}
|
|
|
|
/* Copy ID filter table to Message Buffer Region. */
|
|
for (i = 0; i < config->idFilterNum; i++)
|
|
{
|
|
idFilterRegion[i] = config->idFilterTable[i];
|
|
}
|
|
|
|
/* Setup ID Fitlter Type. */
|
|
switch (config->idFilterType)
|
|
{
|
|
case kFLEXCAN_RxFifoFilterTypeA:
|
|
base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0);
|
|
break;
|
|
case kFLEXCAN_RxFifoFilterTypeB:
|
|
base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1);
|
|
break;
|
|
case kFLEXCAN_RxFifoFilterTypeC:
|
|
base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2);
|
|
break;
|
|
case kFLEXCAN_RxFifoFilterTypeD:
|
|
/* All frames rejected. */
|
|
base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* Setting Message Reception Priority. */
|
|
base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK :
|
|
base->CTRL2 | CAN_CTRL2_MRP_MASK;
|
|
|
|
/* Enable Rx Message FIFO. */
|
|
base->MCR |= CAN_MCR_RFEN_MASK;
|
|
}
|
|
else
|
|
{
|
|
/* Disable Rx Message FIFO. */
|
|
base->MCR &= ~CAN_MCR_RFEN_MASK;
|
|
|
|
/* Clean MB0 ~ MB5. */
|
|
FLEXCAN_SetRxMbConfig(base, 0, NULL, false);
|
|
FLEXCAN_SetRxMbConfig(base, 1, NULL, false);
|
|
FLEXCAN_SetRxMbConfig(base, 2, NULL, false);
|
|
FLEXCAN_SetRxMbConfig(base, 3, NULL, false);
|
|
FLEXCAN_SetRxMbConfig(base, 4, NULL, false);
|
|
FLEXCAN_SetRxMbConfig(base, 5, NULL, false);
|
|
}
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
|
|
#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
|
|
void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
/* Enable FlexCAN DMA. */
|
|
base->MCR |= CAN_MCR_DMA_MASK;
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
else
|
|
{
|
|
/* Enter Freeze Mode. */
|
|
FLEXCAN_EnterFreezeMode(base);
|
|
|
|
/* Disable FlexCAN DMA. */
|
|
base->MCR &= ~CAN_MCR_DMA_MASK;
|
|
|
|
/* Exit Freeze Mode. */
|
|
FLEXCAN_ExitFreezeMode(base);
|
|
}
|
|
}
|
|
#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
|
|
|
|
status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame)
|
|
{
|
|
/* Assertion. */
|
|
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(txFrame);
|
|
assert(txFrame->length <= 8);
|
|
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
|
|
|
uint32_t cs_temp = 0;
|
|
|
|
/* Check if Message Buffer is available. */
|
|
if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
|
|
{
|
|
/* Inactive Tx Message Buffer. */
|
|
base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
|
|
|
/* Fill Message ID field. */
|
|
base->MB[mbIdx].ID = txFrame->id;
|
|
|
|
/* Fill Message Format field. */
|
|
if (kFLEXCAN_FrameFormatExtend == txFrame->format)
|
|
{
|
|
cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK;
|
|
}
|
|
|
|
/* Fill Message Type field. */
|
|
if (kFLEXCAN_FrameTypeRemote == txFrame->type)
|
|
{
|
|
cs_temp |= CAN_CS_RTR_MASK;
|
|
}
|
|
|
|
cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length);
|
|
|
|
/* Load Message Payload. */
|
|
base->MB[mbIdx].WORD0 = txFrame->dataWord0;
|
|
base->MB[mbIdx].WORD1 = txFrame->dataWord1;
|
|
|
|
/* Activate Tx Message Buffer. */
|
|
base->MB[mbIdx].CS = cs_temp;
|
|
|
|
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
|
|
base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
|
base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
|
|
#endif
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
/* Tx Message Buffer is activated, return immediately. */
|
|
return kStatus_Fail;
|
|
}
|
|
}
|
|
|
|
status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
|
|
{
|
|
/* Assertion. */
|
|
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(rxFrame);
|
|
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
|
|
|
uint32_t cs_temp;
|
|
uint8_t rx_code;
|
|
|
|
/* Read CS field of Rx Message Buffer to lock Message Buffer. */
|
|
cs_temp = base->MB[mbIdx].CS;
|
|
/* Get Rx Message Buffer Code field. */
|
|
rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT;
|
|
|
|
/* Check to see if Rx Message Buffer is full. */
|
|
if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code))
|
|
{
|
|
/* Store Message ID. */
|
|
rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK);
|
|
|
|
/* Get the message ID and format. */
|
|
rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard;
|
|
|
|
/* Get the message type. */
|
|
rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData;
|
|
|
|
/* Get the message length. */
|
|
rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT;
|
|
|
|
/* Store Message Payload. */
|
|
rxFrame->dataWord0 = base->MB[mbIdx].WORD0;
|
|
rxFrame->dataWord1 = base->MB[mbIdx].WORD1;
|
|
|
|
/* Read free-running timer to unlock Rx Message Buffer. */
|
|
(void)base->TIMER;
|
|
|
|
if (kFLEXCAN_RxMbFull == rx_code)
|
|
{
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
return kStatus_FLEXCAN_RxOverflow;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Read free-running timer to unlock Rx Message Buffer. */
|
|
(void)base->TIMER;
|
|
|
|
return kStatus_Fail;
|
|
}
|
|
}
|
|
|
|
status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame)
|
|
{
|
|
/* Assertion. */
|
|
assert(rxFrame);
|
|
|
|
uint32_t cs_temp;
|
|
|
|
/* Check if Rx FIFO is Enabled. */
|
|
if (base->MCR & CAN_MCR_RFEN_MASK)
|
|
{
|
|
/* Read CS field of Rx Message Buffer to lock Message Buffer. */
|
|
cs_temp = base->MB[0].CS;
|
|
|
|
/* Read data from Rx FIFO output port. */
|
|
/* Store Message ID. */
|
|
rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK);
|
|
|
|
/* Get the message ID and format. */
|
|
rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard;
|
|
|
|
/* Get the message type. */
|
|
rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData;
|
|
|
|
/* Get the message length. */
|
|
rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT;
|
|
|
|
/* Store Message Payload. */
|
|
rxFrame->dataWord0 = base->MB[0].WORD0;
|
|
rxFrame->dataWord1 = base->MB[0].WORD1;
|
|
|
|
/* Store ID Filter Hit Index. */
|
|
rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK);
|
|
|
|
/* Read free-running timer to unlock Rx Message Buffer. */
|
|
(void)base->TIMER;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
}
|
|
|
|
status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame)
|
|
{
|
|
/* Write Tx Message Buffer to initiate a data sending. */
|
|
if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame))
|
|
{
|
|
/* Wait until CAN Message send out. */
|
|
while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
|
|
{
|
|
}
|
|
|
|
/* Clean Tx Message Buffer Flag. */
|
|
FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
return kStatus_Fail;
|
|
}
|
|
}
|
|
|
|
status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame)
|
|
{
|
|
/* Wait until Rx Message Buffer non-empty. */
|
|
while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx))
|
|
{
|
|
}
|
|
|
|
/* Clean Rx Message Buffer Flag. */
|
|
FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx);
|
|
|
|
/* Read Received CAN Message. */
|
|
return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame);
|
|
}
|
|
|
|
status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame)
|
|
{
|
|
status_t rxFifoStatus;
|
|
|
|
/* Wait until Rx FIFO non-empty. */
|
|
while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag))
|
|
{
|
|
}
|
|
|
|
/* */
|
|
rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame);
|
|
|
|
/* Clean Rx Fifo available flag. */
|
|
FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag);
|
|
|
|
return rxFifoStatus;
|
|
}
|
|
|
|
void FLEXCAN_TransferCreateHandle(CAN_Type *base,
|
|
flexcan_handle_t *handle,
|
|
flexcan_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
uint8_t instance;
|
|
|
|
/* Clean FlexCAN transfer handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Get instance from peripheral base address. */
|
|
instance = FLEXCAN_GetInstance(base);
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
s_flexcanHandle[instance] = handle;
|
|
|
|
/* Register Callback function. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
s_flexcanIsr = FLEXCAN_TransferHandleIRQ;
|
|
|
|
/* We Enable Error & Status interrupt here, because this interrupt just
|
|
* report current status of FlexCAN module through Callback function.
|
|
* It is insignificance without a available callback function.
|
|
*/
|
|
if (handle->callback != NULL)
|
|
{
|
|
FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable |
|
|
kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable |
|
|
kFLEXCAN_WakeUpInterruptEnable);
|
|
}
|
|
else
|
|
{
|
|
FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable |
|
|
kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable |
|
|
kFLEXCAN_WakeUpInterruptEnable);
|
|
}
|
|
|
|
/* Enable interrupts in NVIC. */
|
|
EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance]));
|
|
EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance]));
|
|
EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance]));
|
|
EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance]));
|
|
EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance]));
|
|
EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance]));
|
|
}
|
|
|
|
status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
assert(xfer);
|
|
assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
|
|
|
|
/* Check if Message Buffer is idle. */
|
|
if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
|
|
{
|
|
/* Distinguish transmit type. */
|
|
if (kFLEXCAN_FrameTypeRemote == xfer->frame->type)
|
|
{
|
|
handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote;
|
|
|
|
/* Register user Frame buffer to receive remote Frame. */
|
|
handle->mbFrameBuf[xfer->mbIdx] = xfer->frame;
|
|
}
|
|
else
|
|
{
|
|
handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData;
|
|
}
|
|
|
|
if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame))
|
|
{
|
|
/* Enable Message Buffer Interrupt. */
|
|
FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle;
|
|
return kStatus_Fail;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return kStatus_FLEXCAN_TxBusy;
|
|
}
|
|
}
|
|
|
|
status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
assert(xfer);
|
|
assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx));
|
|
|
|
/* Check if Message Buffer is idle. */
|
|
if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx])
|
|
{
|
|
handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData;
|
|
|
|
/* Register Message Buffer. */
|
|
handle->mbFrameBuf[xfer->mbIdx] = xfer->frame;
|
|
|
|
/* Enable Message Buffer Interrupt. */
|
|
FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
return kStatus_FLEXCAN_RxBusy;
|
|
}
|
|
}
|
|
|
|
status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
assert(xfer);
|
|
|
|
/* Check if Message Buffer is idle. */
|
|
if (kFLEXCAN_StateIdle == handle->rxFifoState)
|
|
{
|
|
handle->rxFifoState = kFLEXCAN_StateRxFifo;
|
|
|
|
/* Register Message Buffer. */
|
|
handle->rxFifoFrameBuf = xfer->frame;
|
|
|
|
/* Enable Message Buffer Interrupt. */
|
|
FLEXCAN_EnableMbInterrupts(
|
|
base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
return kStatus_FLEXCAN_RxFifoBusy;
|
|
}
|
|
}
|
|
|
|
void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
|
|
|
/* Disable Message Buffer Interrupt. */
|
|
FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
|
|
|
|
/* Un-register handle. */
|
|
handle->mbFrameBuf[mbIdx] = 0x0;
|
|
|
|
/* Clean Message Buffer. */
|
|
FLEXCAN_SetTxMbConfig(base, mbIdx, true);
|
|
|
|
handle->mbState[mbIdx] = kFLEXCAN_StateIdle;
|
|
}
|
|
|
|
void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
|
|
assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
|
|
|
|
/* Disable Message Buffer Interrupt. */
|
|
FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx);
|
|
|
|
/* Un-register handle. */
|
|
handle->mbFrameBuf[mbIdx] = 0x0;
|
|
handle->mbState[mbIdx] = kFLEXCAN_StateIdle;
|
|
}
|
|
|
|
void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
|
|
/* Check if Rx FIFO is enabled. */
|
|
if (base->MCR & CAN_MCR_RFEN_MASK)
|
|
{
|
|
/* Disable Rx Message FIFO Interrupts. */
|
|
FLEXCAN_DisableMbInterrupts(
|
|
base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag);
|
|
|
|
/* Un-register handle. */
|
|
handle->rxFifoFrameBuf = 0x0;
|
|
}
|
|
|
|
handle->rxFifoState = kFLEXCAN_StateIdle;
|
|
}
|
|
|
|
void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle)
|
|
{
|
|
/* Assertion. */
|
|
assert(handle);
|
|
|
|
status_t status = kStatus_FLEXCAN_UnHandled;
|
|
uint32_t result;
|
|
|
|
/* Store Current FlexCAN Module Error and Status. */
|
|
result = base->ESR1;
|
|
|
|
do
|
|
{
|
|
/* Solve FlexCAN Error and Status Interrupt. */
|
|
if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
|
|
kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))
|
|
{
|
|
status = kStatus_FLEXCAN_ErrorStatus;
|
|
|
|
/* Clear FlexCAN Error and Status Interrupt. */
|
|
FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag |
|
|
kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag);
|
|
}
|
|
/* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */
|
|
else
|
|
{
|
|
/* For this implementation, we solve the Message with lowest MB index first. */
|
|
for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++)
|
|
{
|
|
/* Get the lowest unhandled Message Buffer */
|
|
if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result)))
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Does not find Message to deal with. */
|
|
if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))
|
|
{
|
|
break;
|
|
}
|
|
|
|
/* Solve Rx FIFO interrupt. */
|
|
if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag))
|
|
{
|
|
switch (1 << result)
|
|
{
|
|
case kFLEXCAN_RxFifoOverflowFlag:
|
|
status = kStatus_FLEXCAN_RxFifoOverflow;
|
|
break;
|
|
|
|
case kFLEXCAN_RxFifoWarningFlag:
|
|
status = kStatus_FLEXCAN_RxFifoWarning;
|
|
break;
|
|
|
|
case kFLEXCAN_RxFifoFrameAvlFlag:
|
|
status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf);
|
|
if (kStatus_Success == status)
|
|
{
|
|
status = kStatus_FLEXCAN_RxFifoIdle;
|
|
}
|
|
FLEXCAN_TransferAbortReceiveFifo(base, handle);
|
|
break;
|
|
|
|
default:
|
|
status = kStatus_FLEXCAN_UnHandled;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get current State of Message Buffer. */
|
|
switch (handle->mbState[result])
|
|
{
|
|
/* Solve Rx Data Frame. */
|
|
case kFLEXCAN_StateRxData:
|
|
status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]);
|
|
if (kStatus_Success == status)
|
|
{
|
|
status = kStatus_FLEXCAN_RxIdle;
|
|
}
|
|
FLEXCAN_TransferAbortReceive(base, handle, result);
|
|
break;
|
|
|
|
/* Solve Rx Remote Frame. */
|
|
case kFLEXCAN_StateRxRemote:
|
|
status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]);
|
|
if (kStatus_Success == status)
|
|
{
|
|
status = kStatus_FLEXCAN_RxIdle;
|
|
}
|
|
FLEXCAN_TransferAbortReceive(base, handle, result);
|
|
break;
|
|
|
|
/* Solve Tx Data Frame. */
|
|
case kFLEXCAN_StateTxData:
|
|
status = kStatus_FLEXCAN_TxIdle;
|
|
FLEXCAN_TransferAbortSend(base, handle, result);
|
|
break;
|
|
|
|
/* Solve Tx Remote Frame. */
|
|
case kFLEXCAN_StateTxRemote:
|
|
handle->mbState[result] = kFLEXCAN_StateRxRemote;
|
|
status = kStatus_FLEXCAN_TxSwitchToRx;
|
|
break;
|
|
|
|
default:
|
|
status = kStatus_FLEXCAN_UnHandled;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Clear resolved Message Buffer IRQ. */
|
|
FLEXCAN_ClearMbStatusFlags(base, 1 << result);
|
|
}
|
|
|
|
/* Calling Callback Function if has one. */
|
|
if (handle->callback != NULL)
|
|
{
|
|
handle->callback(base, handle, status, result, handle->userData);
|
|
}
|
|
|
|
/* Reset return status */
|
|
status = kStatus_FLEXCAN_UnHandled;
|
|
|
|
/* Store Current FlexCAN Module Error and Status. */
|
|
result = base->ESR1;
|
|
}
|
|
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
|
|
while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) ||
|
|
(0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
|
|
kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
|
|
#else
|
|
while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) ||
|
|
(0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag |
|
|
kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag))));
|
|
#endif
|
|
}
|
|
|
|
#if defined(CAN0)
|
|
void CAN0_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[0]);
|
|
|
|
s_flexcanIsr(CAN0, s_flexcanHandle[0]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CAN1)
|
|
void CAN1_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[1]);
|
|
|
|
s_flexcanIsr(CAN1, s_flexcanHandle[1]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CAN2)
|
|
void CAN2_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[2]);
|
|
|
|
s_flexcanIsr(CAN2, s_flexcanHandle[2]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CAN3)
|
|
void CAN3_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[3]);
|
|
|
|
s_flexcanIsr(CAN3, s_flexcanHandle[3]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CAN4)
|
|
void CAN4_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[4]);
|
|
|
|
s_flexcanIsr(CAN4, s_flexcanHandle[4]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA_CAN0)
|
|
void DMA_FLEXCAN0_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]);
|
|
|
|
s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA_CAN1)
|
|
void DMA_FLEXCAN1_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]);
|
|
|
|
s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]);
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA_CAN2)
|
|
void DMA_FLEXCAN2_DriverIRQHandler(void)
|
|
{
|
|
assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]);
|
|
|
|
s_flexcanIsr(DMA_CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]);
|
|
}
|
|
#endif
|