1249 lines
47 KiB
C
1249 lines
47 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_dspi_edma.h"
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/***********************************************************************************************************************
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* Definitons
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***********************************************************************************************************************/
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/*!
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* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private.
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*/
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typedef struct _dspi_master_edma_private_handle
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{
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SPI_Type *base; /*!< DSPI peripheral base address. */
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dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */
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} dspi_master_edma_private_handle_t;
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/*!
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* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private.
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*/
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typedef struct _dspi_slave_edma_private_handle
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{
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SPI_Type *base; /*!< DSPI peripheral base address. */
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dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */
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} dspi_slave_edma_private_handle_t;
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/***********************************************************************************************************************
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* Prototypes
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***********************************************************************************************************************/
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/*!
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* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
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* This is not a public API.
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*/
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static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
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void *g_dspiEdmaPrivateHandle,
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bool transferDone,
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uint32_t tcds);
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/*!
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* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
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* This is not a public API.
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*/
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static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
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void *g_dspiEdmaPrivateHandle,
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bool transferDone,
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uint32_t tcds);
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/*!
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* @brief Get instance number for DSPI module.
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*
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* This is not a public API and it's extern from fsl_dspi.c.
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*
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* @param base DSPI peripheral base address
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*/
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extern uint32_t DSPI_GetInstance(SPI_Type *base);
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/***********************************************************************************************************************
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* Variables
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***********************************************************************************************************************/
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/*! @brief Pointers to dspi edma handles for each instance. */
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static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
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static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
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/***********************************************************************************************************************
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* Code
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***********************************************************************************************************************/
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void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
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dspi_master_edma_handle_t *handle,
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dspi_master_edma_transfer_callback_t callback,
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void *userData,
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edma_handle_t *edmaRxRegToRxDataHandle,
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edma_handle_t *edmaTxDataToIntermediaryHandle,
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edma_handle_t *edmaIntermediaryToTxRegHandle)
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{
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assert(handle);
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assert(edmaRxRegToRxDataHandle);
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assert(edmaTxDataToIntermediaryHandle);
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assert(edmaIntermediaryToTxRegHandle);
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/* Zero the handle. */
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memset(handle, 0, sizeof(*handle));
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uint32_t instance = DSPI_GetInstance(base);
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s_dspiMasterEdmaPrivateHandle[instance].base = base;
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s_dspiMasterEdmaPrivateHandle[instance].handle = handle;
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handle->callback = callback;
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handle->userData = userData;
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handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
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handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle;
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handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle;
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}
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status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer)
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{
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assert(handle);
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assert(transfer);
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/* If the transfer count is zero, then return immediately.*/
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if (transfer->dataSize == 0)
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{
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return kStatus_InvalidArgument;
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}
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/* If both send buffer and receive buffer is null */
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if ((!(transfer->txData)) && (!(transfer->rxData)))
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{
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return kStatus_InvalidArgument;
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}
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/* Check that we're not busy.*/
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if (handle->state == kDSPI_Busy)
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{
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return kStatus_DSPI_Busy;
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}
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handle->state = kDSPI_Busy;
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uint32_t instance = DSPI_GetInstance(base);
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uint16_t wordToSend = 0;
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uint8_t dummyData = DSPI_DUMMY_DATA;
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uint8_t dataAlreadyFed = 0;
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uint8_t dataFedMax = 2;
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uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
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uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base);
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edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU));
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edma_transfer_config_t transferConfigA;
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edma_transfer_config_t transferConfigB;
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edma_transfer_config_t transferConfigC;
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handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
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dspi_command_data_config_t commandStruct;
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DSPI_StopTransfer(base);
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DSPI_FlushFifo(base, true, true);
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DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
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commandStruct.whichPcs =
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(dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT));
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commandStruct.isEndOfQueue = false;
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commandStruct.clearTransferCount = false;
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commandStruct.whichCtar =
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(dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT);
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commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous);
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handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct));
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commandStruct.isEndOfQueue = true;
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commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer);
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handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct));
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handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1;
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if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK))
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{
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handle->fifoSize = 1;
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}
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else
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{
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handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base);
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}
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handle->txData = transfer->txData;
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handle->rxData = transfer->rxData;
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handle->remainingSendByteCount = transfer->dataSize;
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handle->remainingReceiveByteCount = transfer->dataSize;
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handle->totalByteCount = transfer->dataSize;
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/* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
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* due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
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*/
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uint32_t limited_size = 0;
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if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
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{
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limited_size = 32767u;
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}
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else
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{
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limited_size = 511u;
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}
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if (handle->bitsPerFrame > 8)
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{
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if (transfer->dataSize > (limited_size << 1u))
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{
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handle->state = kDSPI_Idle;
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return kStatus_DSPI_OutOfRange;
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}
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}
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else
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{
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if (transfer->dataSize > limited_size)
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{
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handle->state = kDSPI_Idle;
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return kStatus_DSPI_OutOfRange;
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}
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}
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/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
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if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
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{
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handle->state = kDSPI_Idle;
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return kStatus_InvalidArgument;
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}
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DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
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EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
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&s_dspiMasterEdmaPrivateHandle[instance]);
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/*
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(1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
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channel_A minor link to channel_B , channel_B minor link to channel_C.
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Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer.
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channel_A:SPI_POPR to rxData,
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channel_B:next txData to handle->command (low 16 bits),
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channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data
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(handle->lastCommand to SPI_PUSHR).
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(2)For DSPI instances with separate RX and TX DMA requests:
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Rx DMA request -> channel_A
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Tx DMA request -> channel_C -> channel_B .
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channel_C major link to channel_B.
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So need prepare the first data in "intermediary" before the DMA
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transfer and then channel_B is used to prepare the next data to "intermediary"
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channel_A:SPI_POPR to rxData,
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channel_C: handle->command (32 bits) to SPI_PUSHR,
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channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data
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(handle->lastCommand to handle->Command).
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*/
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/*If dspi has separate dma request , prepare the first data in "intermediary" .
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else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
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if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
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{
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/* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to
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* trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel
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*/
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/*Prepare the firt data*/
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if (handle->bitsPerFrame > 8)
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{
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/* If it's the last word */
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if (handle->remainingSendByteCount <= 2)
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{
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if (handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData; /* increment to next data byte */
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wordToSend |= (unsigned)(*(handle->txData)) << 8U;
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}
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else
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{
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wordToSend = ((uint32_t)dummyData << 8) | dummyData;
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}
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handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
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handle->command = handle->lastCommand;
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}
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else /* For all words except the last word , frame > 8bits */
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{
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if (handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData; /* increment to next data byte */
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wordToSend |= (unsigned)(*(handle->txData)) << 8U;
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++handle->txData; /* increment to next data byte */
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}
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else
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{
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wordToSend = ((uint32_t)dummyData << 8) | dummyData;
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}
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handle->command = (handle->command & 0xffff0000U) | wordToSend;
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}
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}
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else /* Optimized for bits/frame less than or equal to one byte. */
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{
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if (handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData; /* increment to next data word*/
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}
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else
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{
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wordToSend = dummyData;
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}
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if (handle->remainingSendByteCount == 1)
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{
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handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
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handle->command = handle->lastCommand;
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}
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else
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{
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handle->command = (handle->command & 0xffff0000U) | wordToSend;
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}
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}
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}
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else /*dspi has shared dma request*/
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{
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/* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
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* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
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*/
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/* If bits/frame is greater than one byte */
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if (handle->bitsPerFrame > 8)
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{
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while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
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{
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if (handle->remainingSendByteCount <= 2)
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{
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if (handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData;
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wordToSend |= (unsigned)(*(handle->txData)) << 8U;
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}
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else
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{
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wordToSend = ((uint32_t)dummyData << 8) | dummyData;
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}
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handle->remainingSendByteCount = 0;
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base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
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}
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/* For all words except the last word */
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else
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{
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if (handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData;
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wordToSend |= (unsigned)(*(handle->txData)) << 8U;
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++handle->txData;
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}
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else
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{
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wordToSend = ((uint32_t)dummyData << 8) | dummyData;
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}
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handle->remainingSendByteCount -= 2;
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base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
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}
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/* Try to clear the TFFF; if the TX FIFO is full this will clear */
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DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
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dataAlreadyFed += 2;
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/* exit loop if send count is zero, else update local variables for next loop */
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if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2)))
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{
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break;
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}
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} /* End of TX FIFO fill while loop */
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}
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else /* Optimized for bits/frame less than or equal to one byte. */
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{
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while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
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{
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if (handle->txData)
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{
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wordToSend = *(handle->txData);
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++handle->txData;
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}
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else
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{
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wordToSend = dummyData;
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}
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if (handle->remainingSendByteCount == 1)
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{
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base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend;
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}
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else
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{
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base->PUSHR = (handle->command & 0xffff0000U) | wordToSend;
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}
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/* Try to clear the TFFF; if the TX FIFO is full this will clear */
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DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
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--handle->remainingSendByteCount;
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dataAlreadyFed++;
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/* exit loop if send count is zero, else update local variables for next loop */
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if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax))
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{
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break;
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}
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} /* End of TX FIFO fill while loop */
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}
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}
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/***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/
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EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
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transferConfigA.srcAddr = (uint32_t)rxAddr;
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transferConfigA.srcOffset = 0;
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if (handle->rxData)
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{
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transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
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transferConfigA.destOffset = 1;
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}
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else
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{
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transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
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transferConfigA.destOffset = 0;
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}
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transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
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if (handle->bitsPerFrame <= 8)
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{
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transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
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transferConfigA.minorLoopBytes = 1;
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transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
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}
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else
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{
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transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
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transferConfigA.minorLoopBytes = 2;
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transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
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}
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/* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
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handle->nbytes = transferConfigA.minorLoopBytes;
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EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
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&transferConfigA, NULL);
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EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
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kEDMA_MajorInterruptEnable);
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/***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
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write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
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SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
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EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
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/*Calculate the last data : handle->lastCommand*/
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if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
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((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
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((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
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(1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
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{
|
|
if (handle->txData)
|
|
{
|
|
uint32_t bufferIndex = 0;
|
|
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
bufferIndex = handle->remainingSendByteCount - 1;
|
|
}
|
|
else
|
|
{
|
|
bufferIndex = handle->remainingSendByteCount - 2;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
bufferIndex = handle->remainingSendByteCount;
|
|
}
|
|
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1];
|
|
}
|
|
else
|
|
{
|
|
handle->lastCommand = (handle->lastCommand & 0xffff0000U) |
|
|
((uint32_t)handle->txData[bufferIndex - 1] << 8) |
|
|
handle->txData[bufferIndex - 2];
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
wordToSend = dummyData;
|
|
}
|
|
else
|
|
{
|
|
wordToSend = ((uint32_t)dummyData << 8) | dummyData;
|
|
}
|
|
handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
|
|
}
|
|
}
|
|
|
|
/*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
|
|
* (handle->lastCommand) to handle->Command*/
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
|
|
transferConfigB.destAddr = (uint32_t) & (handle->command);
|
|
transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigB.srcOffset = 0;
|
|
transferConfigB.destOffset = 0;
|
|
transferConfigB.minorLoopBytes = 4;
|
|
transferConfigB.majorLoopCounts = 1;
|
|
|
|
EDMA_TcdReset(softwareTCD);
|
|
EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
|
|
}
|
|
|
|
/*User_Send_Buffer(txData) to intermediary(handle->command)*/
|
|
if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
|
|
((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) &&
|
|
(1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
|
|
(1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
|
|
{
|
|
if (handle->txData)
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t)(handle->txData);
|
|
transferConfigB.srcOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
|
|
transferConfigB.srcOffset = 0;
|
|
}
|
|
|
|
transferConfigB.destAddr = (uint32_t)(&handle->command);
|
|
transferConfigB.destOffset = 0;
|
|
|
|
transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigB.minorLoopBytes = 1;
|
|
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2;
|
|
}
|
|
else
|
|
{
|
|
/*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
|
|
majorlink , the majorlink would not trigger the channel_C*/
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigB.minorLoopBytes = 2;
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2;
|
|
}
|
|
else
|
|
{
|
|
/*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
|
|
* majorlink*/
|
|
transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
|
|
}
|
|
}
|
|
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD);
|
|
EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, false);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
|
|
}
|
|
|
|
/***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
|
|
handle the last data */
|
|
|
|
EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
|
|
|
|
/*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data
|
|
* (handle->lastCommand) to SPI_PUSHR*/
|
|
if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
|
|
transferConfigC.destAddr = (uint32_t)txAddr;
|
|
transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.srcOffset = 0;
|
|
transferConfigC.destOffset = 0;
|
|
transferConfigC.minorLoopBytes = 4;
|
|
transferConfigC.majorLoopCounts = 1;
|
|
|
|
EDMA_TcdReset(softwareTCD);
|
|
EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL);
|
|
}
|
|
|
|
if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
|
|
((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) ||
|
|
(1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t)(&(handle->command));
|
|
transferConfigC.destAddr = (uint32_t)txAddr;
|
|
|
|
transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes;
|
|
transferConfigC.srcOffset = 0;
|
|
transferConfigC.destOffset = 0;
|
|
transferConfigC.minorLoopBytes = 4;
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
|
|
}
|
|
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.majorLoopCounts = 1;
|
|
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
|
|
}
|
|
|
|
EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, false);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
|
|
}
|
|
|
|
/*Start the EDMA channel_A , channel_B , channel_C transfer*/
|
|
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle);
|
|
EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle);
|
|
|
|
/*Set channel priority*/
|
|
uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
|
|
uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel;
|
|
uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel;
|
|
uint8_t t = 0;
|
|
if (channelPriorityLow > channelPriorityMid)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityMid;
|
|
channelPriorityMid = t;
|
|
}
|
|
|
|
if (channelPriorityLow > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
|
|
if (channelPriorityMid > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityMid;
|
|
channelPriorityMid = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
edma_channel_Preemption_config_t preemption_config_t;
|
|
preemption_config_t.enableChannelPreemption = true;
|
|
preemption_config_t.enablePreemptAbility = true;
|
|
preemption_config_t.channelPriority = channelPriorityLow;
|
|
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityMid;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityMid;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
&preemption_config_t);
|
|
}
|
|
|
|
/*Set the channel link.*/
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
/*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
|
|
to prepare the next 32bits data (txData to handle->command) */
|
|
if (handle->remainingSendByteCount > 1)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
|
|
handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink,
|
|
handle->edmaTxDataToIntermediaryHandle->channel);
|
|
}
|
|
|
|
DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
}
|
|
else
|
|
{
|
|
if (handle->remainingSendByteCount > 0)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel);
|
|
|
|
EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base,
|
|
handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink,
|
|
handle->edmaIntermediaryToTxRegHandle->channel);
|
|
}
|
|
|
|
DSPI_EnableDMA(base, kDSPI_RxDmaEnable);
|
|
}
|
|
|
|
DSPI_StartTransfer(base);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
|
|
void *g_dspiEdmaPrivateHandle,
|
|
bool transferDone,
|
|
uint32_t tcds)
|
|
{
|
|
assert(edmaHandle);
|
|
assert(g_dspiEdmaPrivateHandle);
|
|
|
|
dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle;
|
|
|
|
dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
|
|
|
|
DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
|
|
dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
|
|
|
|
if (dspiEdmaPrivateHandle->handle->callback)
|
|
{
|
|
dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
|
|
kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
|
|
}
|
|
}
|
|
|
|
void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
DSPI_StopTransfer(base);
|
|
|
|
DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
|
|
EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle);
|
|
EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle);
|
|
|
|
handle->state = kDSPI_Idle;
|
|
}
|
|
|
|
status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Catch when there is not an active transfer. */
|
|
if (handle->state != kDSPI_Busy)
|
|
{
|
|
*count = 0;
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
size_t bytes;
|
|
|
|
bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
|
|
handle->edmaRxRegToRxDataHandle->channel);
|
|
|
|
*count = handle->totalByteCount - bytes;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base,
|
|
dspi_slave_edma_handle_t *handle,
|
|
dspi_slave_edma_transfer_callback_t callback,
|
|
void *userData,
|
|
edma_handle_t *edmaRxRegToRxDataHandle,
|
|
edma_handle_t *edmaTxDataToTxRegHandle)
|
|
{
|
|
assert(handle);
|
|
assert(edmaRxRegToRxDataHandle);
|
|
assert(edmaTxDataToTxRegHandle);
|
|
|
|
/* Zero the handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
uint32_t instance = DSPI_GetInstance(base);
|
|
|
|
s_dspiSlaveEdmaPrivateHandle[instance].base = base;
|
|
s_dspiSlaveEdmaPrivateHandle[instance].handle = handle;
|
|
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
|
|
handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle;
|
|
}
|
|
|
|
status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer)
|
|
{
|
|
assert(handle);
|
|
assert(transfer);
|
|
|
|
/* If send/receive length is zero */
|
|
if (transfer->dataSize == 0)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* If both send buffer and receive buffer is null */
|
|
if ((!(transfer->txData)) && (!(transfer->rxData)))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Check that we're not busy.*/
|
|
if (handle->state == kDSPI_Busy)
|
|
{
|
|
return kStatus_DSPI_Busy;
|
|
}
|
|
|
|
handle->state = kDSPI_Busy;
|
|
|
|
uint32_t instance = DSPI_GetInstance(base);
|
|
uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
|
|
handle->bitsPerFrame =
|
|
(((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1;
|
|
|
|
/* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
|
|
* due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
|
|
*/
|
|
uint32_t limited_size = 0;
|
|
if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
limited_size = 32767u;
|
|
}
|
|
else
|
|
{
|
|
limited_size = 511u;
|
|
}
|
|
|
|
if (handle->bitsPerFrame > 8)
|
|
{
|
|
if (transfer->dataSize > (limited_size << 1u))
|
|
{
|
|
handle->state = kDSPI_Idle;
|
|
return kStatus_DSPI_OutOfRange;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (transfer->dataSize > limited_size)
|
|
{
|
|
handle->state = kDSPI_Idle;
|
|
return kStatus_DSPI_OutOfRange;
|
|
}
|
|
}
|
|
|
|
/*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
|
|
if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
|
|
{
|
|
handle->state = kDSPI_Idle;
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
|
|
|
|
/* Store transfer information */
|
|
handle->txData = transfer->txData;
|
|
handle->rxData = transfer->rxData;
|
|
handle->remainingSendByteCount = transfer->dataSize;
|
|
handle->remainingReceiveByteCount = transfer->dataSize;
|
|
handle->totalByteCount = transfer->dataSize;
|
|
|
|
uint16_t wordToSend = 0;
|
|
uint8_t dummyData = DSPI_DUMMY_DATA;
|
|
uint8_t dataAlreadyFed = 0;
|
|
uint8_t dataFedMax = 2;
|
|
|
|
uint32_t rxAddr = DSPI_GetRxRegisterAddress(base);
|
|
uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base);
|
|
|
|
edma_transfer_config_t transferConfigA;
|
|
edma_transfer_config_t transferConfigC;
|
|
|
|
DSPI_StopTransfer(base);
|
|
|
|
DSPI_FlushFifo(base, true, true);
|
|
DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
|
|
|
|
DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
|
|
DSPI_StartTransfer(base);
|
|
|
|
/*if dspi has separate dma request , need not prepare data first .
|
|
else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to
|
|
slaveGetTxRegister if there is no fifo*/
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
/* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
|
|
* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
|
|
*/
|
|
/* If bits/frame is greater than one byte */
|
|
if (handle->bitsPerFrame > 8)
|
|
{
|
|
while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
|
|
{
|
|
if (handle->txData)
|
|
{
|
|
wordToSend = *(handle->txData);
|
|
++handle->txData; /* Increment to next data byte */
|
|
|
|
wordToSend |= (unsigned)(*(handle->txData)) << 8U;
|
|
++handle->txData; /* Increment to next data byte */
|
|
}
|
|
else
|
|
{
|
|
wordToSend = ((uint32_t)dummyData << 8) | dummyData;
|
|
}
|
|
handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */
|
|
base->PUSHR_SLAVE = wordToSend;
|
|
|
|
/* Try to clear the TFFF; if the TX FIFO is full this will clear */
|
|
DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
|
|
|
|
dataAlreadyFed += 2;
|
|
|
|
/* Exit loop if send count is zero, else update local variables for next loop */
|
|
if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2)))
|
|
{
|
|
break;
|
|
}
|
|
} /* End of TX FIFO fill while loop */
|
|
}
|
|
else /* Optimized for bits/frame less than or equal to one byte. */
|
|
{
|
|
while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)
|
|
{
|
|
if (handle->txData)
|
|
{
|
|
wordToSend = *(handle->txData);
|
|
/* Increment to next data word*/
|
|
++handle->txData;
|
|
}
|
|
else
|
|
{
|
|
wordToSend = dummyData;
|
|
}
|
|
|
|
base->PUSHR_SLAVE = wordToSend;
|
|
|
|
/* Try to clear the TFFF; if the TX FIFO is full this will clear */
|
|
DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag);
|
|
/* Decrement remainingSendByteCount*/
|
|
--handle->remainingSendByteCount;
|
|
|
|
dataAlreadyFed++;
|
|
|
|
/* Exit loop if send count is zero, else update local variables for next loop */
|
|
if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax))
|
|
{
|
|
break;
|
|
}
|
|
} /* End of TX FIFO fill while loop */
|
|
}
|
|
}
|
|
|
|
/***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
|
|
if (handle->remainingReceiveByteCount > 0)
|
|
{
|
|
EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
|
|
|
|
transferConfigA.srcAddr = (uint32_t)rxAddr;
|
|
transferConfigA.srcOffset = 0;
|
|
|
|
if (handle->rxData)
|
|
{
|
|
transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]);
|
|
transferConfigA.destOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull);
|
|
transferConfigA.destOffset = 0;
|
|
}
|
|
|
|
transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigA.minorLoopBytes = 1;
|
|
transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount;
|
|
}
|
|
else
|
|
{
|
|
transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigA.minorLoopBytes = 2;
|
|
transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2;
|
|
}
|
|
|
|
/* Store the initially configured eDMA minor byte transfer count into the DSPI handle */
|
|
handle->nbytes = transferConfigA.minorLoopBytes;
|
|
|
|
EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
&transferConfigA, NULL);
|
|
EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
kEDMA_MajorInterruptEnable);
|
|
}
|
|
|
|
if (handle->remainingSendByteCount > 0)
|
|
{
|
|
/***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/
|
|
EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel);
|
|
|
|
transferConfigC.destAddr = (uint32_t)txAddr;
|
|
transferConfigC.destOffset = 0;
|
|
|
|
if (handle->txData)
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0]));
|
|
transferConfigC.srcOffset = 1;
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull);
|
|
transferConfigC.srcOffset = 0;
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
handle->txBuffIfNull = DSPI_DUMMY_DATA;
|
|
}
|
|
else
|
|
{
|
|
handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
|
|
}
|
|
}
|
|
|
|
transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
|
|
if (handle->bitsPerFrame <= 8)
|
|
{
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes;
|
|
transferConfigC.minorLoopBytes = 1;
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount;
|
|
}
|
|
else
|
|
{
|
|
transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes;
|
|
transferConfigC.minorLoopBytes = 2;
|
|
transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2;
|
|
}
|
|
|
|
EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
|
|
&transferConfigC, NULL);
|
|
|
|
EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
|
|
}
|
|
|
|
EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
|
|
|
|
/*Set channel priority*/
|
|
uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
|
|
uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel;
|
|
uint8_t t = 0;
|
|
|
|
if (channelPriorityLow > channelPriorityHigh)
|
|
{
|
|
t = channelPriorityLow;
|
|
channelPriorityLow = channelPriorityHigh;
|
|
channelPriorityHigh = t;
|
|
}
|
|
|
|
edma_channel_Preemption_config_t preemption_config_t;
|
|
preemption_config_t.enableChannelPreemption = true;
|
|
preemption_config_t.enablePreemptAbility = true;
|
|
preemption_config_t.channelPriority = channelPriorityLow;
|
|
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
|
|
&preemption_config_t);
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
|
|
&preemption_config_t);
|
|
|
|
preemption_config_t.channelPriority = channelPriorityHigh;
|
|
EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
&preemption_config_t);
|
|
}
|
|
|
|
/*Set the channel link.
|
|
For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C.
|
|
For DSPI instances with separate RX and TX DMA requests:
|
|
Rx DMA request -> channel_A
|
|
Tx DMA request -> channel_C */
|
|
if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
|
|
{
|
|
if (handle->remainingSendByteCount > 0)
|
|
{
|
|
EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
|
|
kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel);
|
|
}
|
|
DSPI_EnableDMA(base, kDSPI_RxDmaEnable);
|
|
}
|
|
else
|
|
{
|
|
DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
|
|
void *g_dspiEdmaPrivateHandle,
|
|
bool transferDone,
|
|
uint32_t tcds)
|
|
{
|
|
assert(edmaHandle);
|
|
assert(g_dspiEdmaPrivateHandle);
|
|
|
|
dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle;
|
|
|
|
dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle;
|
|
|
|
DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
|
|
dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
|
|
|
|
if (dspiEdmaPrivateHandle->handle->callback)
|
|
{
|
|
dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
|
|
kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
|
|
}
|
|
}
|
|
|
|
void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
DSPI_StopTransfer(base);
|
|
|
|
DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
|
|
|
|
EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle);
|
|
EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle);
|
|
|
|
handle->state = kDSPI_Idle;
|
|
}
|
|
|
|
status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Catch when there is not an active transfer. */
|
|
if (handle->state != kDSPI_Busy)
|
|
{
|
|
*count = 0;
|
|
return kStatus_NoTransferInProgress;
|
|
}
|
|
|
|
size_t bytes;
|
|
|
|
bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base,
|
|
handle->edmaRxRegToRxDataHandle->channel);
|
|
|
|
*count = handle->totalByteCount - bytes;
|
|
|
|
return kStatus_Success;
|
|
}
|