117 lines
3.5 KiB
C
117 lines
3.5 KiB
C
/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef ARCH_H_
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#define ARCH_H_
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/*****************************/
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/* BSP CONTROLLER BASE */
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/*****************************/
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#define INTC_REG_BASE (0xE0200000)
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#define SDC0_REG_BASE (0xE2000000)
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#define SDC1_REG_BASE (0xE2100000)
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#define TVE_REG_BASE (0xE8000000)
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#define VOU_REG_BASE (0xE8100000)
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#define AES_REG_BASE (0xE8200000)
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/*
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#define JPEG_REG_BASE (0xE8300000)
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#define ISPB_REG_BASE (0xEA000000)
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#define ISPF_REG_BASE (0xEA100000)
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#define VPU_REG_BASE (0xEC000000)
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#define VCU_REG_BASE (0xEC100000)
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#define DDRC_REG_BASE (0xED000000)
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*/
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#define DMAC_REG_BASE (0xEE000000)
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#define GMAC_REG_BASE (0xEF000000)
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#define PMU_REG_BASE (0xF0000000)
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#define I2C0_REG_BASE (0xF0200000)
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#define GPIO0_REG_BASE (0xF0300000)
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#define GPIO1_REG_BASE (0xf4000000)
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#define PWM_REG_BASE (0xF0400000)
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#define SPI0_REG_BASE (0xF0500000)
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#define SPI1_REG_BASE (0xF0600000)
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#define UART0_REG_BASE (0xF0700000)
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#define UART1_REG_BASE (0xF0800000)
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/*#define I2S_REG_BASE (0xF0900000)*/
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#define ACODEC_REG_BASE (0xF0A00000)
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#define I2C1_REG_BASE (0xF0B00000)
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#define TMR_REG_BASE (0xF0C00000)
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#define WDT_REG_BASE (0xF0D00000)
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/*
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#define DPHY_REG_BASE (0xF1000000)
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#define MIPIC_REG_BASE (0xF1100000)
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*/
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#define SADC_REG_BASE (0xF1200000)
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typedef enum IRQn
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{
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PAE_IRQn = 0,
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VPU_IRQn = 1,
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ISP_F_IRQn = 2,
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ISP_B_IRQn = 3,
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VOU_IRQn = 4,
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JPEG_IRQn = 5,
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TVE_IRQn = 6,
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TOE_IRQn = 7,
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DDRC_IRQn = 8,
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DMAC_IRQn = 9,
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AES_IRQn = 10,
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MIPIC_IRQn = 11,
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MIPI_WRAP_IRQn = 12,
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PMU_IRQn = 13,
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EMAC_IRQn = 14,
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AXIC0_IRQn = 16,
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AXIC1_IRQn = 17,
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X2H0_IRQn = 18,
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X2H1_IRQn = 19,
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AHBC0_IRQn = 20,
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AHBC1_IRQn = 21,
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SADC_IRQn = 23,
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SDC0_IRQn = 24,
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SDC1_IRQn = 25,
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ACW_IRQn = 26,
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WDT_IRQn = 27,
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SPI0_IRQn = 28,
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SPI1_IRQn = 29,
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UART0_IRQn = 30,
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UART1_IRQn = 31,
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I2S0_IRQn = 32,
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I2S1_IRQn = 33,
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RTC_IRQn = 34,
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PWM_IRQn = 35,
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TMR0_IRQn = 36,
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TMR1_IRQn = 37,
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USB0_IRQn = 38,
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USB1_IRQn = 39,
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GPIO0_IRQn = 40,
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GPIO1_IRQn = 41,
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I2C0_IRQn = 42,
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I2C1_IRQn = 43,
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} IRQn_Type;
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#endif /* ARCH_H_ */
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