357 lines
13 KiB
C
357 lines
13 KiB
C
/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef FH_SDIO_H_
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#define FH_SDIO_H_
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#include <rtthread.h>
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//#define __ASIC_BRANCH__
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enum {
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CTRL = 0x0, /** Control */
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PWREN = 0x4, /** Power-enable */
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CLKDIV = 0x8, /** Clock divider */
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CLKSRC = 0xC, /** Clock source */
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CLKENA = 0x10, /** Clock enable */
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TMOUT = 0x14, /** Timeout */
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CTYPE = 0x18, /** Card type */
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BLKSIZ = 0x1C, /** Block Size */
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BYTCNT = 0x20, /** Byte count */
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INTMSK = 0x24, /** Interrupt Mask */
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CMDARG = 0x28, /** Command Argument */
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CMD = 0x2C, /** Command */
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RESP0 = 0x30, /** Response 0 */
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RESP1 = 0x34, /** Response 1 */
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RESP2 = 0x38, /** Response 2 */
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RESP3 = 0x3C, /** Response 3 */
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MINTSTS = 0x40, /** Masked interrupt status */
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RINTSTS = 0x44, /** Raw interrupt status */
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STATUS = 0x48, /** Status */
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FIFOTH = 0x4C, /** FIFO threshold */
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CDETECT = 0x50, /** Card detect */
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WRTPRT = 0x54, /** Write protect */
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GPIO = 0x58, /** General Purpose IO */
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TCBCNT = 0x5C, /** Transferred CIU byte count */
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TBBCNT = 0x60, /** Transferred host/DMA to/from byte count */
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DEBNCE = 0x64, /** Card detect debounce */
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USRID = 0x68, /** User ID */
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VERID = 0x6C, /** Version ID */
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HCON = 0x70, /** Hardware Configuration */
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UHSREG = 0x74, /** Reserved */
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BMOD = 0x80, /** Bus mode Register */
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PLDMND = 0x84, /** Poll Demand */
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DBADDR = 0x88, /** Descriptor Base Address */
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IDSTS = 0x8C, /** Internal DMAC Status */
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IDINTEN = 0x90, /** Internal DMAC Interrupt Enable */
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DSCADDR = 0x94, /** Current Host Descriptor Address */
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BUFADDR = 0x98, /** Current Host Buffer Address */
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FIFODAT = 0x200, /** FIFO data read write */
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};
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/* Control register definitions */
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#define CTRL_RESET 0x00000001
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#define FIFO_RESET 0x00000002
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#define DMA_RESET 0x00000004
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#define INT_ENABLE 0x00000010
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#define READ_WAIT 0x00000040
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#define CTRL_USE_IDMAC 0x02000000
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/* Interrupt mask defines */
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#define INTMSK_CDETECT 0x00000001
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#define INTMSK_RESP_ERR 0x00000002
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#define INTMSK_CMD_DONE 0x00000004
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#define INTMSK_DAT_OVER 0x00000008
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#define INTMSK_TXDR 0x00000010
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#define INTMSK_RXDR 0x00000020
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#define INTMSK_RCRC 0x00000040
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#define INTMSK_DCRC 0x00000080
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#define INTMSK_RTO 0x00000100
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#define INTMSK_DTO 0x00000200
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#define INTMSK_HTO 0x00000400
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#define INTMSK_VSI INTMSK_HTO // VSI => Voltage Switch Interrupt
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#define INTMSK_FRUN 0x00000800
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#define INTMSK_HLE 0x00001000
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#define INTMSK_SBE 0x00002000
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#define INTMSK_ACD 0x00004000
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#define INTMSK_EBE 0x00008000
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#define INTMSK_SDIO 0x00010000
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#define INTMASK_ERROR (INTMSK_RESP_ERR|INTMSK_RCRC|INTMSK_DCRC|INTMSK_RTO|INTMSK_DTO|INTMSK_HTO|INTMSK_FRUN|INTMSK_HLE|INTMSK_SBE|INTMSK_EBE)
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/*BMOD register define */
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#define BMOD_SWR 0x00000001
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#define BMOD_DE 0x00000080
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/* for STATUS register */
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#define GET_FIFO_COUNT(x) (((x)&0x3ffe0000)>>17)
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#define GET_FIFO_DEPTH(x) ((((x)&0x0FFF0000)>>16)+1)
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/* for IDMA intr register */
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#define IDMAINTBITS 0x337
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/* PMU related registers */
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//#define PMU_REG_BASE 0xF0000000
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#define PMU_REG_RST 0xF0000100
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#define PMU_REG_CLK_DIV3 0xF0000030
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#define PMU_SDC0_RST_BIT 9
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#define PMU_SDC1_RST_BIT 10
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#define PMU_RST_MODULE(x) *((volatile unsigned int*)(PMU_REG_RST)) = (~((1<<(x))))
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/* Define Card status bits (R1 response) */
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#define R1CS_ADDRESS_OUT_OF_RANGE 0x80000000
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#define R1CS_ADDRESS_MISALIGN 0x40000000
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#define R1CS_BLOCK_LEN_ERR 0x20000000
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#define R1CS_ERASE_SEQ_ERR 0x10000000
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#define R1CS_ERASE_PARAM 0x08000000
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#define R1CS_WP_VIOLATION 0x04000000
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#define R1CS_CARD_IS_LOCKED 0x02000000
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#define R1CS_LCK_UNLCK_FAILED 0x01000000
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#define R1CS_COM_CRC_ERROR 0x00800000
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#define R1CS_ILLEGAL_COMMAND 0x00400000
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#define R1CS_CARD_ECC_FAILED 0x00200000
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#define R1CS_CC_ERROR 0x00100000
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#define R1CS_ERROR 0x00080000
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#define R1CS_UNDERRUN 0x00040000
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#define R1CS_OVERRUN 0x00020000
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#define R1CS_CSD_OVERWRITE 0x00010000
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#define R1CS_WP_ERASE_SKIP 0x00008000
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#define R1CS_RESERVED_0 0x00004000
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#define R1CS_ERASE_RESET 0x00002000
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#define R1CS_CURRENT_STATE_MASK 0x00001e00
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#define R1CS_READY_FOR_DATA 0x00000100
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#define R1CS_SWITCH_ERROR 0x00000080
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#define R1CS_RESERVED_1 0x00000040
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#define R1CS_APP_CMD 0x00000020
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#define R1CS_RESERVED_2 0x00000010
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#define R1CS_APP_SPECIFIC_MASK 0x0000000c
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#define R1CS_MANUFAC_TEST_MASK 0x00000003
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#define R1CS_ERROR_OCCURED_MAP 0xfdffa080
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#define R1CS_CURRENT_STATE(x) (((x)&R1CS_CURRENT_STATE_MASK)>>9)
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/* R5 response */
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#define R5_IO_CRC_ERR 0x00008000
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#define R5_IO_BAD_CMD 0x00004000
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#define R5_IO_GEN_ERR 0x00000800
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#define R5_IO_FUNC_ERR 0x00000200
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#define R5_IO_OUT_RANGE 0x00000100
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#define R5_IO_ERR_BITS 0x0000cb00
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enum {
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NONE_TYPE = 0,
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SD_TYPE,
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SD_2_0_TYPE,
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SDIO_TYPE,
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};
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enum {
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CARD_STATE_EMPTY = -1,
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CARD_STATE_IDLE = 0,
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CARD_STATE_READY = 1,
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CARD_STATE_IDENT = 2,
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CARD_STATE_STBY = 3,
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CARD_STATE_TRAN = 4,
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CARD_STATE_DATA = 5,
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CARD_STATE_RCV = 6,
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CARD_STATE_PRG = 7,
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CARD_STATE_DIS = 8,
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CARD_STATE_INA = 9
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};
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enum DmaDescriptorDES1 // Buffer's size field of Descriptor
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{
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DescBuf2SizMsk = 0x03FFE000, /* Mask for Buffer2 Size 25:13 */
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DescBuf2SizeShift = 13, /* Shift value for Buffer2 Size */
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DescBuf1SizMsk = 0x00001FFF, /* Mask for Buffer1 Size 12:0 */
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DescBuf1SizeShift = 0, /* Shift value for Buffer2 Size */
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};
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enum DmaDescriptorDES0 // Control and status word of DMA descriptor DES0
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{
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DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 */
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DescCardErrSummary = 0x40000000, /* Indicates EBE/RTO/RCRC/SBE/DRTO/DCRC/RE 30 */
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DescEndOfRing = 0x00000020, /* A "1" indicates End of Ring for Ring Mode 05 */
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DescSecAddrChained = 0x00000010, /* A "1" indicates DES3 contains Next Desc Address 04 */
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DescFirstDesc = 0x00000008, /* A "1" indicates this Desc contains first 03
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buffer of the data */
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DescLastDesc = 0x00000004, /* A "1" indicates buffer pointed to by this this 02
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Desc contains last buffer of Data */
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DescDisInt = 0x00000002, /* A "1" in this field disables the RI/TI of IDSTS 01
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for data that ends in the buffer pointed to by
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this descriptor */
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};
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typedef struct DmaDescStruct {
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unsigned int desc0; /* control and status information of descriptor */
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unsigned int desc1; /* buffer sizes */
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unsigned int desc2; /* physical address of the buffer 1 */
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unsigned int desc3; /* physical address of the buffer 2 */
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}DmaDesc;
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typedef struct {
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unsigned int wkmod;
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volatile DmaDesc *pDmaDesc;
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unsigned int idma_support;
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unsigned int rca;
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unsigned int ip_base;
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unsigned int card_type;
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unsigned int fifo_depth;
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unsigned int fifo_threth;
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unsigned int sectors;
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unsigned int scr[2];
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unsigned int csd[4];
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unsigned int idsts;
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rt_sem_t sem;
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rt_sem_t mutex;
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void (*cb)(void);
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} sdc_t;
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#define ONE_BIT_MODE (0)
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#define FOUR_BIT_MODE (1)
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#define BE32_TO_CPU(x) ((unsigned int)( \
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(((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
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(((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
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(((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
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(((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24)))
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#define synopmob_set_bits(reg, bit_id) *((volatile unsigned int *)(reg)) |= ((unsigned int)(bit_id))
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#define synopmob_clear_bits(reg, bit_id) *((volatile unsigned int *)(reg)) &= (~((unsigned int)(bit_id)))
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#define synopmob_set_register(reg, val) *((volatile unsigned int*)(reg)) = (val)
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#define synopmob_read_register(reg) (*((volatile unsigned int*)(reg)))
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enum {
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ERRNOERROR = 0,
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// for raw interrupt status error
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ERRRESPRECEP, // 1
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ERRRESPCRC,
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ERRDCRC,
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ERRRESPTIMEOUT,
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ERRDRTIMEOUT,
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ERRUNDERWRITE,
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ERROVERREAD,
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ERRHLE,
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ERRSTARTBIT,
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ERRENDBITERR, // 10
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// for R1 response
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ERRADDRESSRANGE, // 11
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ERRADDRESSMISALIGN,
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ERRBLOCKLEN,
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ERRERASESEQERR,
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ERRERASEPARAM,
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ERRPROT,
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ERRCARDLOCKED,
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ERRCRC,
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ERRILLEGALCOMMAND,
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ERRECCFAILED,
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ERRCCERR,
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ERRUNKNOWN,
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ERRUNDERRUN,
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ERROVERRUN,
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ERRCSDOVERWRITE,
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ERRERASERESET,
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ERRFSMSTATE, // 27
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// for R5 response
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ERRBADFUNC, // 28
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// others
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ERRCARDNOTCONN, // 29
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ERRCARDWPROTECT,
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ERRCMDRETRIESOVER,
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ERRNOTSUPPORTED,
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ERRHARDWARE,
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ERRDATANOTREADY,
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ERRCARDINTERNAL,
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ERRACMD41TIMEOUT,
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ERRIDMA,
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ERRNORES,
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ERRNOTEQUAL,
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};
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#ifdef __ASIC_BRANCH__
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#define SDC_WHERE() *((volatile unsigned int*)0x9b800000) = ((unsigned int)(__LINE__))
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#define SDC_ERROR() do { *((volatile unsigned int*)0x9b800008)=ret; *((volatile unsigned int*)0x9a7ff000) = 0;}while(0)
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#define SDC_FINISH() *((volatile unsigned int*)0x9a7ff004) = 0;
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#else
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#define SDC_WHERE()
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#define SDC_ERROR()
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#define SDC_FINISH()
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#endif //__ASIC_BRANCH__
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#define SDC_WKMOD_25M_STAND_SPEED 0x0002 // 25M standard speed
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#define SDC_WKMOD_50M_HI_SPEED 0x0004 // 50M high speed
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#define SDC_WKMOD_1WIRE 0x0008 // 1 wire transfer mode
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#define SDC_WKMOD_4WIRE 0x0010 // 4 wire transfer mode
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#define SDC_RW_USE_DMA 0x80000000 // Use DMA transfer?
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typedef void* HSDC;
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// map to DmaDesc
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typedef struct _buf_chain {
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unsigned int csi; // desc0
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unsigned int size; // desc1
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void * buf; // desc2
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struct _buf_chain *next; // desc3
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}buf_chain_t;
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/*
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* for SD card
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*/
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extern int sdc_is_connected(unsigned int which);
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extern int sdc_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc/*4Byte aligned,16 bytes space*/, HSDC* phandle);
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extern int sdc_read_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer);
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extern int sdc_write_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer);
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extern int sdc_erase_block(HSDC handle, unsigned int blk, unsigned int num);
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extern int sdc_get_sector_num(HSDC handle);
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extern int sdc_set_clk_divider(unsigned int divider);
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/*
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* for SDIO WIFI card
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*/
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extern void fh_sdio0_init(void);
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extern void fh_sdio1_init(void);
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extern void fh_sdio_init(void);
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extern int sdio_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc/*4Byte aligned,16 bytes space*/, HSDC* phandle);
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extern int sdio_high_speed_mode(HSDC handle, int bitwidth, int freq);
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extern int sdio_enable_card_int(HSDC handle, int enable);
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extern int sdio_set_card_int_cb(HSDC handle, void (*cb)(void));
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extern int sdio_drv_read(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, unsigned char *buf);
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extern int sdio_drv_write(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, unsigned char *buf);
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extern int sdio_drv_creg_read(HSDC handle, int addr, int fn, unsigned int *resp);
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extern int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data, unsigned int *resp);
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extern void inv_dcache_range(unsigned long start, unsigned long len);
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extern void flush_dcache_range(unsigned long start, unsigned long len);
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#endif //__sdcard_h__
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