149 lines
5.3 KiB
C
149 lines
5.3 KiB
C
/*
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* File : bsp.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2006-09-15 QiuYi the first version */
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#ifndef __BSP_H_
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#define __BSP_H_
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#include <i386.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*******************************************************************/
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/* Timer Register */
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/*******************************************************************/
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#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
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#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
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#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
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#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
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#define TIMER_SEL0 0x00 /* select counter 0 */
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#define TIMER_SEL1 0x40 /* select counter 1 */
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#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
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#define TIMER_ONESHOT 0x02 /* mode 1, one shot */
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#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
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#define TIMER_SQWAVE 0x06 /* mode 3, square wave */
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#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
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#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
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#define TIMER_LATCH 0x00 /* latch counter for reading */
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#define TIMER_LSB 0x10 /* r/w counter LSB */
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#define TIMER_MSB 0x20 /* r/w counter MSB */
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#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
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#define TIMER_BCD 0x01 /* count in BCD */
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#define TIMER_FREQ 1193182
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#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
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#define IO_TIMER1 0x040 /* 8253 Timer #1 */
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/*******************************************************************/
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/* Interrupt Controller */
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/*******************************************************************/
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/* these are processor defined */
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#define T_DIVIDE 0 /* divide error */
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#define T_DEBUG 1 /* debug exception */
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#define T_NMI 2 /* non-maskable interrupt */
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#define T_BRKPT 3 /* breakpoint */
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#define T_OFLOW 4 /* overflow */
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#define T_BOUND 5 /* bounds check */
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#define T_ILLOP 6 /* illegal opcode */
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#define T_DEVICE 7 /* device not available */
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#define T_DBLFLT 8 /* double fault */
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/* 9 is reserved */
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#define T_TSS 10 /* invalid task switch segment */
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#define T_SEGNP 11 /* segment not present */
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#define T_STACK 12 /* stack exception */
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#define T_GPFLT 13 /* genernal protection fault */
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#define T_PGFLT 14 /* page fault */
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/* 15 is reserved */
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#define T_FPERR 16 /* floating point error */
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#define T_ALIGN 17 /* aligment check */
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#define T_MCHK 18 /* machine check */
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#define T_DEFAULT 500 /* catchall */
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#define INTTIMER0 0
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#define INTKEYBOARD 1
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#define INTUART0_RX 4
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#define CLOCK_IRQ 0
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#define KEYBOARD_IRQ 1
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#define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */
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#define ETHER_IRQ 3 /* default ethernet interrupt vector */
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#define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */
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#define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */
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#define XT_WINI_IRQ 5 /* xt winchester */
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#define FLOPPY_IRQ 6 /* floppy disk */
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#define PRINTER_IRQ 7
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#define AT_WINI_IRQ 14 /* at winchester */
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/* I/O Addresses of the two 8259A programmable interrupt controllers */
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#define IO_PIC1 0x20 /* Master(IRQs 0-7) */
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#define IO_PIC2 0xa0 /* Slave(IRQs 8-15) */
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#define IRQ_SLAVE 0x2 /* IRQ at which slave connects to master */
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#define IRQ_OFFSET 0x20 /* IRQ 0 corresponds to int IRQ_OFFSET */
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#define MAX_HANDLERS 16 /*max number of isr handler*/
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/*******************************************************************/
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/* CRT Register */
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/*******************************************************************/
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#define MONO_BASE 0x3b4
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#define MONO_BUF 0xb0000
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#define CGA_BASE 0x3d4
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#define CGA_BUF 0xb8000
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#define CRT_ROWS 25
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#define CRT_COLS 80
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#define CRT_SIZE (CRT_ROWS * CRT_COLS)
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/*******************************************************************/
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/* Keyboard Register */
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/*******************************************************************/
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#define KBSTATP 0x64 /* kbd controller status port(I) */
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#define KBS_DIB 0x01 /* kbd data in buffer */
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#define KBDATAP 0x60 /* kbd data port(I) */
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/* AT keyboard */
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/* 8042 ports */
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#define KB_DATA 0x60 /* I/O port for keyboard data
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Read : Read Output Buffer
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Write: Write Input Buffer(8042 Data&8048 Command) */
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#define KB_CMD 0x64 /* I/O port for keyboard command
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Read : Read Status Register
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Write: Write Input Buffer(8042 Command) */
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#define LED_CODE 0xED
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#define KB_ACK 0xFA
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/*******************************************************************/
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/* Serial Register */
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/*******************************************************************/
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/*Serial I/O code */
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#define COM1 0x3F8
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#define COMSTATUS 5
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#define COMDATA 0x01
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#define COMREAD 0
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#define COMWRITE 0
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/* Bits definition of the Line Status Register (LSR)*/
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* Transmitter Holding Register Empty */
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#define TEMT 0x40 /* Transmitter Empty */
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#define ERFIFO 0x80 /* Error receive Fifo */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BSP_H_ */
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