71 lines
1.8 KiB
Plaintext
71 lines
1.8 KiB
Plaintext
#------------------------------------------------
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# SDRAM initialization script for the ASM9260T
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#------------------------------------------------
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define __setup_PLL
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echo "Enabling PLL for CPU" \n
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# outl(1<<2, REG_SET(HW_AHBCLKCTRL0));
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set *0x80040024 = 0x00000004
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# outl(1<<8, REG_SET(HW_AHBCLKCTRL1));
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set *0x80040034 = 0x00000100
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# outl(3<<9, REG_SET(HW_AHBCLKCTRL0));
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set *0x80040024 = 0x00000600
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# outl(inl(HW_PDRUNCFG)&0xFFFFFFFA, HW_PDRUNCFG);
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set *0x80040238 = 0x00000770
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# outl(2, HW_CPUCLKDIV);
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set *0x8004017C = 0x00000002
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# outl(2, HW_SYSAHBCLKDIV);
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set *0x80040180 = 0x00000002
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# outl(480, HW_SYSPLLCTRL);
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set *0x80040100 = 0x000001E0
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# __delay(50)
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set $i = 0
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while $i != 500
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set $i += 1
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end
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# outl(1, HW_MAINCLKSEL);
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set *0x80040120 = 0x00000001
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# outl(0, HW_MAINCLKUEN);
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set *0x80040124 = 0x00000000
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# outl(1, HW_MAINCLKUEN);
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set *0x80040124 = 0x00000001
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end
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define __setup_SDRAM
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echo "Enabling on-chip SDRAM" \n
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# outl((1<<6), REG_SET(HW_AHBCLKCTRL0));
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set *0x80040024 = 0x00000040
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# outl(0x00001188, HW_EMI_SCONR);
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set *0x80700000 = 0x00001188
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# outl(0x000a0500, HW_EMI_CTRL);
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set *0x8004034c = 0x000a0500
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# outl(0x20000000, HW_EMI_SCSLR2_LOW);
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set *0x8070001c = 0x20000000
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# outl(0x0000000c, HW_EMI_SMSKR2);
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set *0x8070005c = 0x0000000c
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# outl(0x024996d9, HW_EMI_STMG0R);
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set *0x80700004 = 0x024996d9
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# outl(0x00542b4f, HW_EMI_SMTMGR_SET0);
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set *0x80700094 = 0x00542b4f
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# outl(0x00003288, HW_EMI_SCTLR);
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set *0x8070000c = 0x00003288
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end
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# Step1: Connect to the J-Link gdb server
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define reset
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#target remote localhost:2331
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monitor reset
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# Step2: Reset peripheral (RSTC_CR)
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echo "------- Prepare for debug ASM9260T -------" \n
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__setup_PLL
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__setup_SDRAM
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# Step3: Load file(eg. getting-started project)
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load
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mon reg pc=0x20000000
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#info reg
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end |