165 lines
3.7 KiB
C
165 lines
3.7 KiB
C
/*
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* File : clock.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://openlab.rt-thread.com/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2013-7-16 Peng Fan Just put the file here, should be implemented in
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* future
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*/
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#include <rtthread.h>
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#include <sep6200.h>
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#define PLL_CFG(_f, _r) {.f = _f, .r = _r} /*f(frequency, MHz); r(config register value)*/
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#define MHz 1000000UL
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/*
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*SEP0611_CLOCK
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*├── APLL
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*│ └── CPU
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*├── DPLL
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*│ └── DDR
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*└── MPLL
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* └── BUS1
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* ├── BUS2
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* │ ├── DMAC1
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* │ ├── ESRAM
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* │ ├── LCDC
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* │ ├── NAND
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* │ ├── NOR
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* │ ├── SDIO1
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* │ ├── SDIO2
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* │ └── VPU
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* ├── BUS3
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* │ ├── BUS5
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* │ │ ├── I2C1
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* │ │ ├── I2C2
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* │ │ ├── I2C3
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* │ │ ├── I2S
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* │ │ ├── SPI1
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* │ │ ├── SPI2
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* │ │ ├── SPI3
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* │ │ ├── UART1
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* │ │ ├── UART2
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* │ │ ├── UART3
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* │ │ └── UART4
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* │ ├── DMAC2
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* │ ├── GPU
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* │ └── USB
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* ├── BUS4
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* │ ├── GPIO
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* │ ├── GPSCTRL
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* │ ├── PWM
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* │ ├── RTC
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* │ ├── SYSCTRL
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* │ ├── TIMER
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* │ └── VIC
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* ├── DS1_2
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* ├── DS1_3
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* └── GPS
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*/
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enum sep0611_clk_gate{
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DDRC = 0, BUS1, BUS2, BUS3, DS1_2,
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DS1_3, USBC, DMAC1, NAND, DMAC2,
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ESRAM, SDIO1, SDIO2, GPU, VPU,
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BUS4, BUS5, VIC_, SYSCTRL, PRTC,
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TIMER, GPSCTRL, GPIO, LCDC2HDMI, DDRPHY,
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UART1, UART2, UART3, UART4, SPI1,
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SPI2, SPI3,
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I2C1 = 32, I2C2, I2C3, I2S, PWM,
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H2X, LCDC, NOR, GPSHCLK, GPS,
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};
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typedef struct {
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unsigned long f;
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unsigned long r;
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}pll_t;
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static pll_t apll_tab[] = {
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PLL_CFG(800*MHz, 0x00010810),
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};
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static pll_t mpll_tab[] = {
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PLL_CFG(480*MHz, 0x00013C12), // 480MHz
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};
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static pll_t dpll_tab[] = {
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PLL_CFG(400*MHz, 0x00010812), // 402MHz
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};
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static void rt_hw_set_system_clock(void)
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{
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/*apll, mpll, dpll is set in uboot when system boots up*/
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}
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static void rt_hw_set_usb_clock(void)
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{
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}
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static void rt_hw_set_peripheral_clock(void)
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{
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}
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/**
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* @brief System Clock Configuration
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*/
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/* apll mpll dpll should be set in u-boot, Here just set clock
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* of the pherial
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*/
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void rt_hw_set_apll_clock(void)
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{
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}
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void rt_hw_set_mpll_clock(void)
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{
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}
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void rt_hw_set_dpll_clock(void)
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{
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}
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void rt_hw_clock_init(void)
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{
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/* set system clock */
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rt_hw_set_system_clock();
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}
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/**
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* @brief Get system clock
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*/
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rt_uint32_t rt_hw_get_clock(void)
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{
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}
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/**
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* @brief Enable module clock
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*/
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void rt_hw_enable_module_clock(rt_uint8_t module)
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{
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if (module >= 32) {
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write_reg(SEP6200_PMU_CLK_GT_CFG2, (1 << (module - 32)) | read_reg(SEP6200_PMU_CLK_GT_CFG2));
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} else {
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write_reg(SEP6200_PMU_CLK_GT_CFG1, (1 << module) | read_reg(SEP6200_PMU_CLK_GT_CFG1));
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}
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}
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/**
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* @brief Disable module clock
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*/
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void rt_hw_disable_module_clock(rt_uint8_t module)
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{
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if (module >= 32) {
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write_reg(SEP6200_PMU_CLK_GT_CFG2, ~(1 << (module - 32)) & read_reg(SEP6200_PMU_CLK_GT_CFG2));
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} else {
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write_reg(SEP6200_PMU_CLK_GT_CFG1, ~(1 << module) & read_reg(SEP6200_PMU_CLK_GT_CFG1));
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}
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}
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