204 lines
6.3 KiB
C
204 lines
6.3 KiB
C
/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-05-17 ZYH first implementation
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*/
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#include <rtthread.h>
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#include "board.h"
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#include "drv_mpu.h"
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#include "drv_sdram.h"
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#include <rthw.h>
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/**
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* @addtogroup STM32
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*/
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static void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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/**Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 432;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 9;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/**Activate the Over-Drive mode
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*/
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HAL_PWREx_EnableOverDrive();
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
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|RCC_PERIPHCLK_USART6|RCC_PERIPHCLK_UART4
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|RCC_PERIPHCLK_UART5|RCC_PERIPHCLK_UART7
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|RCC_PERIPHCLK_SDMMC2|RCC_PERIPHCLK_CLK48;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
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PeriphClkInitStruct.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1;
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PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1;
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PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
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PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1;
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PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
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PeriphClkInitStruct.Sdmmc2ClockSelection = RCC_SDMMC2CLKSOURCE_CLK48;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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}
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
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{
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/**Configure the Systick interrupt time
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*/
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
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/**Configure the Systick
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*/
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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/* SysTick_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
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return HAL_OK;
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}
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uint32_t HAL_GetTick(void)
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{
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return rt_tick_get() * 1000 / RT_TICK_PER_SECOND;
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}
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void HAL_Delay(__IO uint32_t Delay)
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{
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rt_thread_delay(Delay * 1000 / RT_TICK_PER_SECOND);
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}
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void HAL_SuspendTick(void)
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{
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/* we should not suspend tick */
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}
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void HAL_ResumeTick(void)
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{
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/* we should not resume tick */
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}
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#if defined(BSP_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
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static struct rt_memheap system_heap;
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#endif
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void HAL_MspInit(void)
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{
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HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
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/* System interrupt init*/
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/* MemoryManagement_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
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/* BusFault_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
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/* UsageFault_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
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/* SVCall_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
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/* DebugMonitor_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
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/* PendSV_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
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/* SysTick_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
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}
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/**
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* This function will initial STM32 board.
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*/
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void rt_hw_board_init()
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{
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/* Configure the MPU attributes as Write Through */
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bsp_mpu_hw_init();
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/* Enable I-Cache-------------------------------------------------------------*/
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rt_hw_cpu_icache_enable();
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/* Enable D-Cache-------------------------------------------------------------*/
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rt_hw_cpu_dcache_enable();
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/* STM32F7xx HAL library initialization:
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- Configure the Flash ART accelerator on ITCM interface
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- Configure the Systick to generate an interrupt each 1 msec
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- Set NVIC Group Priority to 4
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- Global MSP (MCU Support Package) initialization
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*/
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/* Configure the system clock @ 216 Mhz */
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SystemClock_Config();
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HAL_Init();
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#ifdef RT_USING_HEAP
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#if defined(BSP_USING_SDRAM) && defined(RT_USING_MEMHEAP_AS_HEAP)
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bsp_sdram_hw_init();
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rt_system_heap_init((void *)SDRAM_BEGIN, (void *)SDRAM_END);
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rt_memheap_init(&system_heap, "sram", (void *)HEAP_BEGIN, HEAP_SIZE);
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#else
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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