153 lines
3.7 KiB
C
153 lines
3.7 KiB
C
/*
|
|
* File : interrupt.c
|
|
* This file is part of RT-Thread RTOS
|
|
* COPYRIGHT (C) 2013-2014, RT-Thread Development Team
|
|
*
|
|
* The license and distribution terms for this file may be
|
|
* found in the file LICENSE in this distribution or at
|
|
* http://www.rt-thread.org/license/LICENSE
|
|
*
|
|
* Change Logs:
|
|
* Date Author Notes
|
|
* 2013-07-06 Bernard first version
|
|
* 2014-04-03 Grissiom port to VMM
|
|
*/
|
|
|
|
#include <rthw.h>
|
|
#include <rtthread.h>
|
|
|
|
#include <irq_numbers.h>
|
|
#include <interrupt.h>
|
|
|
|
#include <gic.h>
|
|
#include "cp15.h"
|
|
|
|
#define MAX_HANDLERS IMX_INTERRUPT_COUNT
|
|
|
|
extern volatile rt_uint8_t rt_interrupt_nest;
|
|
|
|
/* exception and interrupt handler table */
|
|
struct rt_irq_desc isr_table[MAX_HANDLERS];
|
|
|
|
rt_uint32_t rt_interrupt_from_thread;
|
|
rt_uint32_t rt_interrupt_to_thread;
|
|
rt_uint32_t rt_thread_switch_interrupt_flag;
|
|
|
|
extern void rt_cpu_vector_set_base(unsigned int addr);
|
|
extern int system_vectors;
|
|
|
|
/* keep compatible with platform SDK */
|
|
void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
|
|
{
|
|
rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, NULL, "unknown");
|
|
}
|
|
|
|
void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
|
|
{
|
|
gic_set_irq_priority(irq_id, priority);
|
|
gic_set_irq_security(irq_id, false); // set IRQ as non-secure
|
|
gic_set_cpu_target(irq_id, cpu_id, true);
|
|
gic_enable_irq(irq_id, true);
|
|
}
|
|
|
|
void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
|
|
{
|
|
gic_enable_irq(irq_id, false);
|
|
gic_set_cpu_target(irq_id, cpu_id, false);
|
|
}
|
|
|
|
static void rt_hw_vector_init(void)
|
|
{
|
|
int sctrl;
|
|
unsigned int *src = (unsigned int *)&system_vectors;
|
|
|
|
/* C12-C0 is only active when SCTLR.V = 0 */
|
|
asm volatile ("mrc p15, #0, %0, c1, c0, #0"
|
|
:"=r" (sctrl));
|
|
sctrl &= ~(1 << 13);
|
|
asm volatile ("mcr p15, #0, %0, c1, c0, #0"
|
|
:
|
|
:"r" (sctrl));
|
|
|
|
asm volatile ("mcr p15, #0, %0, c12, c0, #0"
|
|
:
|
|
:"r" (src));
|
|
}
|
|
|
|
/**
|
|
* This function will initialize hardware interrupt
|
|
*/
|
|
void rt_hw_interrupt_init(void)
|
|
{
|
|
rt_hw_vector_init();
|
|
gic_init();
|
|
|
|
/* init interrupt nest, and context in thread sp */
|
|
rt_interrupt_nest = 0;
|
|
rt_interrupt_from_thread = 0;
|
|
rt_interrupt_to_thread = 0;
|
|
rt_thread_switch_interrupt_flag = 0;
|
|
}
|
|
|
|
/**
|
|
* This function will mask a interrupt.
|
|
* @param vector the interrupt number
|
|
*/
|
|
void rt_hw_interrupt_mask(int vector)
|
|
{
|
|
disable_interrupt(vector, 0);
|
|
}
|
|
|
|
/**
|
|
* This function will un-mask a interrupt.
|
|
* @param vector the interrupt number
|
|
*/
|
|
void rt_hw_interrupt_umask(int vector)
|
|
{
|
|
enable_interrupt(vector, 0, 0);
|
|
}
|
|
|
|
/**
|
|
* This function will install a interrupt service routine to a interrupt.
|
|
* @param vector the interrupt number
|
|
* @param new_handler the interrupt service routine to be installed
|
|
* @param old_handler the old interrupt service routine
|
|
*/
|
|
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
|
void *param, char *name)
|
|
{
|
|
rt_isr_handler_t old_handler = RT_NULL;
|
|
|
|
if (vector < MAX_HANDLERS)
|
|
{
|
|
old_handler = isr_table[vector].handler;
|
|
|
|
if (handler != RT_NULL)
|
|
{
|
|
#ifdef RT_USING_INTERRUPT_INFO
|
|
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
|
#endif /* RT_USING_INTERRUPT_INFO */
|
|
isr_table[vector].handler = handler;
|
|
isr_table[vector].param = param;
|
|
}
|
|
// arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
|
|
}
|
|
|
|
return old_handler;
|
|
}
|
|
|
|
/**
|
|
* Trigger a software IRQ
|
|
*
|
|
* Since we are running in single core, the target CPU are always CPU0.
|
|
*/
|
|
void rt_hw_interrupt_trigger(int vector)
|
|
{
|
|
// arm_gic_trigger(0, 1, vector);
|
|
}
|
|
|
|
void rt_hw_interrupt_clear(int vector)
|
|
{
|
|
gic_write_end_of_irq(vector);
|
|
}
|