141 lines
3.2 KiB
ArmAsm
141 lines
3.2 KiB
ArmAsm
/*
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* File : arm_entry_gcc.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2014-11-07 weety first version
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*/
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#include <rtconfig.h>
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#include "armv6.h"
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//#define DEBUG
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.macro PRINT, str
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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add r0, pc, #4
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bl rt_kprintf
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b 1f
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.asciz "UNDEF: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro PRINT1, str, arg
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r1, \arg
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add r0, pc, #4
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bl rt_kprintf
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b 1f
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.asciz "UNDEF: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro PRINT3, str, arg1, arg2, arg3
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#ifdef DEBUG
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stmfd sp!, {r0-r3, ip, lr}
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mov r3, \arg3
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mov r2, \arg2
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mov r1, \arg1
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add r0, pc, #4
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bl rt_kprintf
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b 1f
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.asciz "UNDEF: \str\n"
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.balign 4
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1: ldmfd sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro get_current_thread, rd
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ldr \rd, .current_thread
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ldr \rd, [\rd]
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.endm
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.current_thread:
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.word rt_current_thread
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#ifdef RT_USING_NEON
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.align 6
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/* is the neon instuction on arm mode? */
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.neon_opcode:
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.word 0xfe000000 @ mask
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.word 0xf2000000 @ opcode
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.word 0xff100000 @ mask
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.word 0xf4000000 @ opcode
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.word 0x00000000 @ end mask
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.word 0x00000000 @ end opcode
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#endif
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/* undefined instruction exception processing */
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.globl undef_entry
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undef_entry:
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PRINT1 "r0=0x%08x", r0
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PRINT1 "r2=0x%08x", r2
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PRINT1 "r9=0x%08x", r9
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PRINT1 "sp=0x%08x", sp
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#ifdef RT_USING_NEON
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ldr r6, .neon_opcode
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__check_neon_instruction:
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ldr r7, [r6], #4 @ load mask value
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cmp r7, #0 @ end mask?
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beq __check_vfp_instruction
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and r8, r0, r7
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ldr r7, [r6], #4 @ load opcode value
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cmp r8, r7 @ is NEON instruction?
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bne __check_neon_instruction
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b vfp_entry
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__check_vfp_instruction:
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#endif
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tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC instruction has bit 27
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tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 instruction
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moveq pc, lr @ no vfp coprocessor instruction, return
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get_current_thread r10
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and r8, r0, #0x00000f00 @ get coprocessor number
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PRINT1 "CP=0x%08x", r8
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add pc, pc, r8, lsr #6
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nop
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mov pc, lr @ CP0
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mov pc, lr @ CP1
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mov pc, lr @ CP2
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mov pc, lr @ CP3
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mov pc, lr @ CP4
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mov pc, lr @ CP5
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mov pc, lr @ CP6
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mov pc, lr @ CP7
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mov pc, lr @ CP8
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mov pc, lr @ CP9
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mov pc, lr @ CP10 VFP
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mov pc, lr @ CP11 VFP
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mov pc, lr @ CP12
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mov pc, lr @ CP13
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mov pc, lr @ CP14 DEBUG
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mov pc, lr @ CP15 SYS CONTROL
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