403 lines
13 KiB
C
403 lines
13 KiB
C
/**
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* \file
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*
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* \brief DFLL management
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*
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* Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef CLK_DFLL_H_INCLUDED
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#define CLK_DFLL_H_INCLUDED
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#include <parts.h>
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#include "conf_clock.h"
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#if UC3L
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# include "uc3l/dfll.h"
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#elif SAM4L
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# include "sam4l/dfll.h"
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#else
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# error Unsupported chip type
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#endif
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/**
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* \ingroup clk_group
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* \defgroup dfll_group DFLL Management
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*
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* A Digital Frequency Locked Loop can be used to generate a highly
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* accurate frequency from a slower-running reference clock, in much the
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* same way as a PLL. DFLLs typically have shorter startup times and
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* less jitter. They can also be used in open-loop mode to generate a
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* less accurate frequency without the use of a reference clock.
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*
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* There may be significant variations between platforms in the support
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* for certain features.
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*
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* \par Example: Setting up DFLL0 with default parameters and dithering enabled
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*
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* The following example shows how to configure and enable DFLL0 in
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* closed-loop mode using the default parameters specified through
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* configuration symbols.
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* \code
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dfll_enable_config_defaults(0); \endcode
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*
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* To configure and enable DFLL0 in closed-loop mode using the default
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* parameters and to enable specific feature like dithering for better accuracy,
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* you can use this initialization process.
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* \code
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struct dfll_config dfllcfg;
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dfll_enable_source(CONFIG_DFLL0_SOURCE);
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dfll_config_defaults(&dfllcfg, 0);
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dfll_config_enable_dithering(&dfllcfg);
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dfll_enable(&dfllcfg, 0);
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dfll_wait_for_accurate_lock(0); \endcode
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*
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* When the last function call returns, DFLL0 is running at a frequency
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* which matches the default configuration as accurately as possible.
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* Any additional alterations to the default configuration can be added
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* at the same place as the call to dfll_config_enable_dithering(), but
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* note that the DFLL will never achieve "accurate" lock if dithering is
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* disabled.
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*
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* @{
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*/
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//! \name Chip-specific DFLL characteristics
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//@{
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/**
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* \def NR_DFLLS
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* \brief Number of on-chip DFLLs.
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*/
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/**
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* \def DFLL_MIN_HZ
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* \brief Minimum frequency that the DFLL can generate.
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*/
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/**
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* \def DFLL_MAX_HZ
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* \brief Maximum frequency that the DFLL can generate.
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*/
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//@}
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/**
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* \typedef dfll_refclk_t
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* \brief Type used for identifying a reference clock source for the DFLL.
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*/
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//! \name DFLL Configuration
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//@{
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/**
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* \struct dfll_config
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* \brief Hardware-specific representation of DFLL configuration.
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*
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* This structure contains one or more device-specific values
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* representing the current DFLL configuration. The contents of this
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* structure is typically different from platform to platform, and the
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* user should not access any fields except through the DFLL
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* configuration API.
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*/
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/**
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* \fn void dfll_config_init_open_loop_mode(struct dfll_config *cfg)
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* \brief Configure the DFLL configuration \a cfg for open-loop mode.
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*
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* \param cfg The DFLL configuration to be initialized.
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*/
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/**
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* \fn void dfll_config_init_closed_loop_mode(struct dfll_config *cfg,
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* dfll_refclk_t refclk, uint16_t div, uint16_t mul)
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* \brief Configure the DFLL configuration \a cfg for closed-loop mode.
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*
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* \param cfg The DFLL configuration to be initialized.
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* \param refclk The reference clock source.
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* \param div Reference clock divider.
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* \param mul Multiplier (integer part only).
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*/
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/**
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* \def dfll_config_defaults(cfg, dfll_id)
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* \brief Initialize DFLL configuration using default parameters.
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*
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* After this function returns, \a cfg will contain a configuration
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* which will make the DFLL run at (CONFIG_DFLLx_MUL / CONFIG_DFLLx_DIV)
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* times the frequency of CONFIG_DFLLx_SOURCE. The default configuration
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* will always use closed-loop mode with no fractional multiplier.
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*
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* \param cfg The DFLL configuration to be initialized.
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* \param dfll_id Use defaults for this DFLL.
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*/
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/**
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* \def dfll_get_default_rate(dfll_id)
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* \brief Return the default rate in Hz of \a dfll_id.
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*/
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/**
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* \fn void dfll_config_set_fractional_multiplier(struct dfll_config *cfg,
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* uint16_t mul_i, uint16_t mul_f)
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* \brief Set a fractional multiplier.
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*
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* This function has no effect in open-loop mode, and is only available
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* on devices which support fractional multipliers.
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*
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* The fractional part of the multiplier is assumed to be 16 bits. The
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* low-level driver will make sure to shift this value to match the
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* hardware if necessary.
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*
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* \param cfg The DFLL configuration to be modified.
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* \param mul_i Integer part of multiplier.
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* \param mul_f Fractional part of multiplier.
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*/
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/**
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* \fn void dfll_config_enable_dithering(struct dfll_config *cfg)
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* \brief Enable dithering for more accurate frequency generation.
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*
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* The fine LSB input to the VCO is dithered to achieve fractional
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* approximation to the correct multiplication ratio.
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*
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* \param cfg The DFLL configuration to be modified.
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*/
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/**
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* \fn void dfll_config_disable_dithering(struct dfll_config *cfg)
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* \brief Disable dithering.
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*
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* \see dfll_config_enable_dithering()
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*
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* \param cfg The DFLL configuration to be modified.
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*/
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/**
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* \fn void dfll_config_set_initial_tuning(struct dfll_config *cfg,
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* uint16_t coarse, uint16_t fine)
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* \brief Set initial VCO tuning.
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*
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* In open loop mode, this will determine the frequency of the output.
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*
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* In closed loop mode, this will provide an initial estimate of the VCO
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* tuning. While the DFLL will automatically adjust these values to
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* match the desired output frequency, careful selection of initial
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* values might reduce the time to achieve coarse and fine lock.
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*
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* \param cfg The DFLL configuration to be modified.
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* \param coarse Coarse tuning of the frequency generator.
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* \param fine Fine tuning of the frequency generator.
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*/
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/**
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* \fn void dfll_config_set_max_step(struct dfll_config *cfg,
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* uint16_t coarse, uint16_t fine)
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* \brief Set the maximum VCO tuning step size.
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*
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* This function has no effect in open-loop mode.
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*
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* By default, both of these values are set to 50% of their respective
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* maximums. It is not recommended to set the values any higher than
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* this, but setting them lower might reduce the frequency overshoot at
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* the expense of longer time to achieve coarse and/or fine lock.
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*
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* \param cfg The DFLL configuration to be modified
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* \param coarse The maximum step size of the coarse VCO tuning.
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* \param fine The maximum step size of the fine VCO tuning.
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*/
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/**
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* \fn void dfll_config_enable_ssg(struct dfll_config *cfg,
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* uint16_t amplitude, uint16_t step_size)
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* \brief Enable Spread Spectrum Generator.
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*
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* \param cfg The DFLL configuration to be modified.
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* \param amplitude The amplitude of the spread spectrum.
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* \param step_size The step size of the spread spectrum.
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*/
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/**
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* \fn void dfll_config_disable_ssg(struct dfll_config *cfg)
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* \brief Disable Spread Spectrum Generator.
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*
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* \param cfg The DFLL configuration to be modified.
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*/
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//@}
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//! \name Interaction with the DFLL hardware
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//@{
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/**
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* \fn void dfll_enable_open_loop(const struct dfll_config *cfg,
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* unsigned int dfll_id)
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* \brief Activate the configuration \a cfg and enable DFLL \a dfll_id
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* in open-loop mode.
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*
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* \pre The configuration in \a cfg must represent an open-loop
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* configuration.
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*
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* \param cfg The configuration to be activated.
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* \param dfll_id The ID of the DFLL to be enabled.
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*/
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/**
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* \fn void dfll_enable_closed_loop(const struct dfll_config *cfg,
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* unsigned int dfll_id)
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* \brief Activate the configuration \a cfg and enable DFLL \a dfll_id
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* in closed-loop mode.
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*
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* \pre The configuration in \a cfg must represent a closed-loop
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* configuration.
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*
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* \param cfg The configuration to be activated.
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* \param dfll_id The ID of the DFLL to be enabled.
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*/
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/**
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* \fn void dfll_disable_open_loop(unsigned int dfll_id)
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* \brief Disable the DFLL identified by \a dfll_id.
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*
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* \pre The DFLL must have been enabled in open loop mode.
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*
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* \param dfll_id The ID of the DFLL to be disabled.
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*/
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/**
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* \fn void dfll_disable_closed_loop(unsigned int dfll_id)
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* \brief Disable the DFLL identified by \a dfll_id.
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*
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* \pre The DFLL must have been enabled in closed loop mode.
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*
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* \param dfll_id The ID of the DFLL to be disabled.
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*/
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/**
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* \fn bool dfll_is_coarse_locked(unsigned int dfll_id)
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* \brief Determine whether or not a DFLL has achieved coarse lock.
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*
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* \param dfll_id The ID of the DFLL to check.
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*
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* \retval true The DFLL has determined the final value of the coarse
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* VCO tuning value.
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* \retval false The DFLL has not yet determined the coarse VCO tuning
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* value, or has not been enabled.
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*/
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/**
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* \fn bool dfll_is_fine_locked(unsigned int dfll_id)
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* \brief Determine whether or not a DFLL has achieved fine lock.
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*
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* \param dfll_id The ID of the DFLL to check.
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*
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* \retval true The DFLL has determined the final value of the fine VCO
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* tuning value.
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* \retval false The DFLL has not yet determined the fine VCO tuning
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* value, or has not been enabled.
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*/
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/**
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* \fn bool dfll_is_accurate_locked(unsigned int dfll_id)
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* \brief Determine whether or not a DFLL has achieved accurate lock.
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*
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* \param dfll_id The ID of the DFLL to check.
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*
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* \retval true The DFLL has determined the final dithering duty cycle.
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* \retval false The DFLL has not yet determined the dithering duty
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* cycle, or has not been enabled with dithering enabled.
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*/
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/**
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* \fn void dfll_enable_source(enum dfll_refclk_t src)
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* \brief Enable the source of the dfll.
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* The source is enabled, if the source is not already running.
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*
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* \param dfll_source src The ID of the DFLL source to enable.
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*/
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/**
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* \fn void dfll_enable_config_defaults(unsigned int dfll_id)
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* \brief Enable the dfll with the default configuration.
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* DFLL is enabled, if the DFLL is not already locked.
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*
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* \param dfll_id The ID of the DFLL to enable.
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*/
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/**
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* \brief Wait for the DFLL identified by \a dfll_id to achieve coarse
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* lock.
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*
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* \param dfll_id The ID of the DFLL to wait for.
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*
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* \retval STATUS_OK The DFLL has achieved coarse lock.
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* \retval ERR_TIMEOUT Timed out waiting for lock.
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*/
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static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id)
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{
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/* TODO: Add timeout mechanism */
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while (!dfll_is_coarse_locked(dfll_id)) {
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/* Do nothing */
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}
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return 0;
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}
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/**
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* \brief Wait for the DFLL identified by \a dfll_id to achieve fine
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* lock.
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*
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* \param dfll_id The ID of the DFLL to wait for.
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*
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* \retval STATUS_OK The DFLL has achieved fine lock.
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* \retval ERR_TIMEOUT Timed out waiting for lock.
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*/
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static inline int dfll_wait_for_fine_lock(unsigned int dfll_id)
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{
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/* TODO: Add timeout mechanism */
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while (!dfll_is_fine_locked(dfll_id)) {
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/* Do nothing */
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}
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return 0;
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}
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/**
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* \brief Wait for the DFLL identified by \a dfll_id to achieve accurate
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* lock.
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*
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* \param dfll_id The ID of the DFLL to wait for.
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*
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* \retval STATUS_OK The DFLL has achieved accurate lock.
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* \retval ERR_TIMEOUT Timed out waiting for lock.
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*/
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static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id)
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{
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/* TODO: Add timeout mechanism */
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while (!dfll_is_accurate_locked(dfll_id)) {
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/* Do nothing */
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}
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return 0;
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}
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//@}
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//! @}
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#endif /* CLK_DFLL_H_INCLUDED */
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