550 lines
14 KiB
C
550 lines
14 KiB
C
/*
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* File : rtthread.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2012, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE.
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*
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* Change Logs:
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* Date Author Notes
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* 2011-10-13 prife the first version
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* 2012-03-11 prife use mtd device interface
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*/
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#include <rtdevice.h>
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#include <s3c24x0.h>
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//#include "nand.h"
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// For flash chip that is bigger than 32 MB, we need to have 4 step address
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//
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#define NFCONF_INIT 0xF830 // 512-byte 4 Step Address
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#define NEED_EXT_ADDR 1
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//#define NFCONF_INIT 0xA830 // 256-byte 4 Step Address
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//#define NEED_EXT_ADDR 0
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//#define NFCONF_INIT 0xF840
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// NAND Flash Command. This appears to be generic across all NAND flash chips
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#define CMD_READ 0x00 // Read
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#define CMD_READ1 0x01 // Read1
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#define CMD_READ2 0x50 // Read2
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#define CMD_READ3 0x30 // Read3
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#define CMD_READID 0x90 // ReadID
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#define CMD_WRITE1 0x80 // Write phase 1
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#define CMD_WRITE2 0x10 // Write phase 2
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#define CMD_ERASE1 0x60 // Erase phase 1
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#define CMD_ERASE2 0xd0 // Erase phase 2
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#define CMD_STATUS 0x70 // Status read
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#define CMD_RESET 0xff // Reset
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#define CMD_RANDOMREAD1 0x05 // random read phase 1
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#define CMD_RANDOMREAD2 0xE0 // random read phase 2
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#define CMD_RANDOMWRITE 0x85 // random write phase 1
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#define NF_CMD(cmd) {NFCMD = (cmd); }
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#define NF_ADDR(addr) {NFADDR = (addr); }
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#define NF_nFCE_L() {NFCONT &= ~(1<<1); }
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#define NF_nFCE_H() {NFCONT |= (1<<1); }
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#define NF_RSTECC() {NFCONT |= (1<<4); }
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#define NF_RDMECC() (NFMECC0 )
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#define NF_RDSECC() (NFSECC )
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#define NF_RDDATA() (NFDATA)
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#define NF_RDDATA8() (NFDATA8)
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#define NF_WRDATA(data) {NFDATA = (data); }
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#define NF_WRDATA8(data) {NFDATA8 = (data); }
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#define NF_WAITRB() {while(!(NFSTAT&(1<<0)));}
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#define NF_CLEAR_RB() {NFSTAT |= (1<<2); }
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#define NF_DETECT_RB() {while(!(NFSTAT&(1<<2)));}
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#define NF_MECC_UnLock() {NFCONT &= ~(1<<5); }
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#define NF_MECC_Lock() {NFCONT |= (1<<5); }
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#define NF_SECC_UnLock() {NFCONT &= ~(1<<6); }
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#define NF_SECC_Lock() {NFCONT |= (1<<6); }
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#define RdNFDat8() (NFDATA8) //byte access
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#define RdNFDat() RdNFDat8() //for 8 bit nand flash, use byte access
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#define WrNFDat8(dat) (NFDATA8 = (dat)) //byte access
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#define WrNFDat(dat) WrNFDat8() //for 8 bit nand flash, use byte access
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#define NF_CE_L() NF_nFCE_L()
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#define NF_CE_H() NF_nFCE_H()
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#define NF_DATA_R() NFDATA
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#define NF_ECC() NFECC0
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// HCLK=100Mhz
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#define TACLS 1 // 1-clk(0ns)
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#define TWRPH0 4 // 3-clk(25ns)
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#define TWRPH1 0 // 1-clk(10ns) //TACLS+TWRPH0+TWRPH1>=50ns
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// Status bit pattern
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#define STATUS_READY 0x40 // Ready
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#define STATUS_ERROR 0x01 // Error
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#define STATUS_ILLACC 0x08 // Illigar Access
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//
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// ERROR_Xxx
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//
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#define ERR_SUCCESS 0
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#define ERR_DISK_OP_FAIL1 1
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#define ERR_DISK_OP_FAIL2 2
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#define ERR_INVALID_BOOT_SECTOR 3
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#define ERR_INVALID_LOAD_ADDR 4
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#define ERR_GEN_FAILURE 5
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#define ERR_INVALID_PARAMETER 6
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#define ERR_JUMP_FAILED 7
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#define ERR_INVALID_TOC 8
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#define ERR_INVALID_FILE_TYPE 9
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//#define NF_READID 1
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#define READ_SECTOR_INFO
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#define NAND_BASE 0xB0E00000
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#define IOP_BASE 0xB1600000
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#define PAGE_DATA_SIZE 2048
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static struct rt_mutex nand;
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/*
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* In a page, data's ecc code is stored in spare area, spare BYTE0 to BYTEE 3
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* block's status byte which indicate a block is bad is BYTE4 in spare area
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*/
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static void nand_hw_init(void)
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{
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/* Init GPIO<49><4F> nFWE<57><45>ALE<4C><45>CLE<4C><45>nFCE<43><45>nFRE */
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GPACON |= (1<<17) | (1<<18) | (1<<19) | (1<<20) | (1<<22);
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/* Enable PCLK into nand Controller */
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CLKCON |= 1 << 4;
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NFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
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NFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
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NFSTAT = 0;
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/* reset nand flash */
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NF_CE_L();
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NF_CLEAR_RB();
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NF_CMD(CMD_RESET);
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NF_DETECT_RB();
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NF_CE_H();
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}
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static rt_err_t k9f1g08_mtd_erase_block(
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struct rt_mtd_nand_device* device,
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rt_uint32_t block)
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{
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/* 1 block = 64 page= 2^6*/
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rt_err_t result = RT_EOK;
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block <<= 6; /* get the first page's address in this block*/
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rt_mutex_take(&nand, RT_WAITING_FOREVER);
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NF_nFCE_L(); /* enable chip */
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NF_CLEAR_RB();
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NF_CMD(CMD_ERASE1); /* Erase one block 1st command */
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NF_ADDR(block & 0xff);
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NF_ADDR((block >> 8) & 0xff);
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// NF_ADDR((block >> 16) & 0xff);
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NF_CMD(CMD_ERASE2);
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NF_DETECT_RB(); /* Wait for ready bit */
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if ( NFSTAT & STATUS_ILLACC )
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{
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NFSTAT |= STATUS_ILLACC; /* Write 1 to clear.*/
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result = -RT_ERROR;
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} else {
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NF_CMD(CMD_STATUS); /* Check the status */
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if (NF_DATA_R() & STATUS_ERROR) {
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result = -RT_ERROR;
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}
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}
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NF_nFCE_H();
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rt_mutex_release(&nand);
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return result;
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/* TODO: more check about status */
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}
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/* return 0, ecc ok, 1, can be fixed , -1 can not be fixed */
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static rt_err_t k9f1g08_mtd_read(
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struct rt_mtd_nand_device * dev,
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rt_off_t page,
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rt_uint8_t * data, rt_uint32_t data_len, //may not always be 2048
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rt_uint8_t * spare, rt_uint32_t spare_len)
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{
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rt_uint32_t i;
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rt_uint32_t mecc;
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rt_uint32_t status;
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rt_err_t result;
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rt_mutex_take(&nand, RT_WAITING_FOREVER);
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NF_RSTECC(); /* reset ECC*/
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NF_MECC_UnLock();/* unlock MECC */
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NF_nFCE_L(); /* enable chip */
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if (data != RT_NULL && data_len != 0)
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{
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/* read page data area */
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NF_CLEAR_RB();
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NF_CMD(CMD_READ);
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NF_ADDR(0);
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NF_ADDR(0);
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NF_ADDR((page) & 0xff);
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NF_ADDR((page >> 8) & 0xff);
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// NF_ADDR((page >> 16) & 0xff);
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NF_CMD(CMD_READ3);
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NF_DETECT_RB();/* Wait for RB */
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/*TODO: use a more quick method */
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for (i = 0; i < data_len; i++)
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data[i] = NF_RDDATA8();
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NF_MECC_Lock();
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/* if read whole page data, then check ecc status */
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if (data_len == PAGE_DATA_SIZE)
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{
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mecc = NF_RDDATA();
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NFMECCD0 = ((mecc&0xff00)<<8)|(mecc&0xff);
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NFMECCD1 = ((mecc&0xff000000)>>8)|((mecc&0xff0000)>>16);
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/* check data ecc */
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status = NFESTAT0 & 0x03;
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if (status == 0x00)
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result = RT_EOK; /* no error */
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else if (status == 0x01)
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result = -1;/* error can be fixed */
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else
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result = -2; /* erroe can't be fixed */
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}
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else
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result = RT_EOK;
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}
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if (spare != RT_NULL && spare_len != 0)
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{
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/* read page spare area */
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NF_CLEAR_RB();
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NF_CMD(CMD_READ);
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NF_ADDR(PAGE_DATA_SIZE);
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NF_ADDR((PAGE_DATA_SIZE >> 8) & 0xff);
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NF_ADDR((page) & 0xff);
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NF_ADDR((page >> 8) & 0xff);
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// NF_ADDR((page >> 16) & 0xff);
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NF_CMD(CMD_READ3);
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NF_DETECT_RB();/* Wait for RB */
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/*TODO: use a more quick method */
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for (i = 0; i < spare_len; i++)
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spare[i] = NF_RDDATA8();
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NF_MECC_Lock();
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result = RT_EOK;
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}
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NF_nFCE_H();
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rt_mutex_release(&nand);
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return result;
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}
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static rt_err_t k9f1g08_mtd_write (
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struct rt_mtd_nand_device * dev,
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rt_off_t page,
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const rt_uint8_t * data, rt_uint32_t data_len,//will be 2048 always!
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const rt_uint8_t * spare, rt_uint32_t spare_len)
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{
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rt_uint32_t i;
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rt_uint32_t mecc0;
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rt_err_t result = RT_EOK;
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rt_uint8_t ecc_data[4];
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rt_mutex_take(&nand, RT_WAITING_FOREVER);
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NF_nFCE_L(); /* enable chip */
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NF_RSTECC();
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NF_MECC_UnLock();
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if (data != RT_NULL && data_len != 0)
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{
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RT_ASSERT(data_len == PAGE_DATA_SIZE);
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NF_CLEAR_RB(); /* clear RB */
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NF_CMD(CMD_WRITE1);
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NF_ADDR(0);
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NF_ADDR(0);
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NF_ADDR( page & 0xff);
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NF_ADDR((page >> 8) & 0xff);
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// NF_ADDR((page >> 16) & 0xff);
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for(i=0; i<PAGE_DATA_SIZE; i++) //PAGE_DATA_SIZE
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NF_WRDATA8(data[i]);
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NF_MECC_Lock();
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/* produce HARDWARE ECC */
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mecc0=NFMECC0;
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ecc_data[0]=(rt_uint8_t)(mecc0 & 0xff);
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ecc_data[1]=(rt_uint8_t)((mecc0 >> 8) & 0xff);
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ecc_data[2]=(rt_uint8_t)((mecc0 >> 16) & 0xff);
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ecc_data[3]=(rt_uint8_t)((mecc0 >> 24) & 0xff);
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/* write ecc to spare[0]..[3] */
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for(i=0; i<4; i++)
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NF_WRDATA8(ecc_data[i]);
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NF_CMD(CMD_WRITE2);
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NF_DETECT_RB(); /* Wait for RB */
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if (NFSTAT & STATUS_ILLACC)
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{
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NFSTAT |= STATUS_ILLACC;
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result = -RT_ERROR;
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goto __ret;
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}
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else
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{
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NF_CMD(CMD_STATUS);
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if (NF_DATA_R() & STATUS_ERROR)
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{
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result = -RT_ERROR;
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goto __ret;
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}
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}
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}
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if (spare != RT_NULL && spare_len != 0)
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{
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NF_CLEAR_RB();
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NF_CMD(CMD_WRITE1);
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NF_ADDR(PAGE_DATA_SIZE);
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NF_ADDR((PAGE_DATA_SIZE >> 8) & 0xff);
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NF_ADDR( page & 0xff);
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NF_ADDR((page >> 8) & 0xff);
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// NF_ADDR((page >> 16) & 0xff);
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for(i=0; i<spare_len; i++)
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NF_WRDATA8(spare[i]);
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NF_CMD(CMD_WRITE2);
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NF_DETECT_RB();
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if (NFSTAT & STATUS_ILLACC)
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{
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NFSTAT |= STATUS_ILLACC;
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result = -RT_ERROR;
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goto __ret;
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}
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else
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{
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NF_CMD(CMD_STATUS);
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if (NF_DATA_R() & STATUS_ERROR)
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{
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result = -RT_ERROR;
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goto __ret;
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}
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}
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}
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__ret:
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NF_nFCE_H(); /* disable chip */
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rt_mutex_release(&nand);
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return result;
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}
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static rt_err_t k9f1g08_read_id(
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struct rt_mtd_nand_device * dev)
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{
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return RT_EOK;
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}
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const static struct rt_mtd_nand_driver_ops k9f1g08_mtd_ops =
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{
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k9f1g08_read_id,
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k9f1g08_mtd_read,
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k9f1g08_mtd_write,
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k9f1g08_mtd_erase_block,
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};
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/* interface of nand and rt-thread device */
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static struct rt_mtd_nand_device nand_part[4];
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void k9f1g08_mtd_init()
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{
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/* initialize nand controller of S3C2440 */
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nand_hw_init();
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/* initialize mutex */
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if (rt_mutex_init(&nand, "nand", RT_IPC_FLAG_FIFO) != RT_EOK)
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{
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rt_kprintf("init nand lock mutex failed\n");
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}
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/* the first partition of nand */
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nand_part[0].page_size = PAGE_DATA_SIZE;
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nand_part[0].block_size = PAGE_DATA_SIZE*64;//don't caculate oob size
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nand_part[0].block_start = 0;
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nand_part[0].block_end = 255;
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nand_part[0].oob_size = 64;
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nand_part[0].ops = &k9f1g08_mtd_ops;
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rt_mtd_nand_register_device("nand0", &nand_part[0]);
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/* the second partition of nand */
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nand_part[1].page_size = PAGE_DATA_SIZE;
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nand_part[1].block_size = PAGE_DATA_SIZE*64;//don't caculate oob size
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nand_part[1].block_start = 256;
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nand_part[1].block_end = 512-1;
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nand_part[1].oob_size = 64;
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nand_part[1].ops = &k9f1g08_mtd_ops;
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rt_mtd_nand_register_device("nand1", &nand_part[1]);
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/* the third partition of nand */
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nand_part[2].page_size = PAGE_DATA_SIZE;
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nand_part[2].block_size = PAGE_DATA_SIZE*64;//don't caculate oob size
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nand_part[2].block_start = 512;
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nand_part[2].block_end = 512+256-1;
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nand_part[2].oob_size = 64;
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nand_part[2].ops = &k9f1g08_mtd_ops;
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rt_mtd_nand_register_device("nand2", &nand_part[2]);
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/* the 4th partition of nand */
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nand_part[3].page_size = PAGE_DATA_SIZE;
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nand_part[3].block_size = PAGE_DATA_SIZE*64;//don't caculate oob size
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nand_part[3].block_start = 512+256;
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nand_part[3].block_end = 1024-1;
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nand_part[3].oob_size = 64;
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nand_part[3].ops = &k9f1g08_mtd_ops;
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rt_mtd_nand_register_device("nand3", &nand_part[3]);
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}
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#include "finsh.h"
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static char buf[PAGE_DATA_SIZE+64];
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static char spare[64];
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void nand_erase(int start, int end)
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{
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int page;
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for(; start <= end; start ++)
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{
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page = start * 64;
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rt_memset(buf, 0, PAGE_DATA_SIZE);
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rt_memset(spare, 0, 64);
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k9f1g08_mtd_erase_block(RT_NULL, start);
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k9f1g08_mtd_read(RT_NULL, page, buf, PAGE_DATA_SIZE, spare, 64);
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if (spare[0] != 0xFF)
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{
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rt_kprintf("block %d is bad, mark it bad\n", start);
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//rt_memset(spare, 0xFF, 64);
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if (spare[4] == 0xFF)
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{
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spare[4] = 0x00;
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k9f1g08_mtd_write(RT_NULL, page, RT_NULL, 0, spare, 64);
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}
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}
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}
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}
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int nand_read(int page)
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{
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int i;
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int res;
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rt_memset(buf, 0, sizeof(buf));
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// rt_memset(spare, 0, 64);
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// res = k9f1g08_mtd_read(RT_NULL, page, buf, PAGE_DATA_SIZE, spare, 64);
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res = k9f1g08_mtd_read(RT_NULL, page, buf, PAGE_DATA_SIZE+64, RT_NULL, 0);
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rt_kprintf("block=%d, page=%d\n", page/64, page%64);
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for(i=0; i<PAGE_DATA_SIZE; i++)
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{
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rt_kprintf("%02x ", buf[i]);
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if((i+1)%16 == 0)
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rt_kprintf("\n");
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}
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rt_kprintf("spare:\n");
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for(i=0; i<64; i++)
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{
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// rt_kprintf("%02x ", spare[i]);
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rt_kprintf("%02x ", buf[2048+i]);
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if((i+1)%8 == 0)
|
||
rt_kprintf("\n");
|
||
}
|
||
return res;
|
||
}
|
||
int nand_write(int page)
|
||
{
|
||
int i;
|
||
rt_memset(buf, 0, PAGE_DATA_SIZE);
|
||
for(i=0; i<PAGE_DATA_SIZE; i++)
|
||
buf[i] = (i % 2) + i / 2;
|
||
return k9f1g08_mtd_write(RT_NULL, page, buf, PAGE_DATA_SIZE, RT_NULL, 0);
|
||
}
|
||
|
||
int nand_read2(int page)
|
||
{
|
||
int i;
|
||
int res;
|
||
rt_memset(buf, 0, sizeof(buf));
|
||
|
||
res = k9f1g08_mtd_read(RT_NULL, page, buf, PAGE_DATA_SIZE, RT_NULL, 0);
|
||
rt_kprintf("block=%d, page=%d\n", page/64, page%64);
|
||
for(i=0; i<PAGE_DATA_SIZE; i++)
|
||
{
|
||
rt_kprintf("%02x ", buf[i]);
|
||
if((i+1)%16 == 0)
|
||
rt_kprintf("\n");
|
||
}
|
||
|
||
rt_memset(spare, 0, 64);
|
||
res = k9f1g08_mtd_read(RT_NULL, page, RT_NULL, 0, spare, 64);
|
||
rt_kprintf("spare:\n");
|
||
for(i=0; i<64; i++)
|
||
{
|
||
rt_kprintf("%02x ", spare[i]);
|
||
if((i+1)%8 == 0)
|
||
rt_kprintf("\n");
|
||
}
|
||
return res;
|
||
}
|
||
int nand_read3(int page)
|
||
{
|
||
int i;
|
||
int res;
|
||
rt_memset(buf, 0, sizeof(buf));
|
||
rt_memset(spare, 0, 64);
|
||
|
||
res = k9f1g08_mtd_read(RT_NULL, page, buf, PAGE_DATA_SIZE, spare, 64);
|
||
rt_kprintf("block=%d, page=%d\n", page/64, page%64);
|
||
for(i=0; i<PAGE_DATA_SIZE; i++)
|
||
{
|
||
rt_kprintf("%02x ", buf[i]);
|
||
if((i+1)%16 == 0)
|
||
rt_kprintf("\n");
|
||
}
|
||
|
||
rt_kprintf("spare:\n");
|
||
for(i=0; i<64; i++)
|
||
{
|
||
rt_kprintf("%02x ", spare[i]);
|
||
if((i+1)%8 == 0)
|
||
rt_kprintf("\n");
|
||
}
|
||
return res;
|
||
}
|
||
FINSH_FUNCTION_EXPORT(nand_read, nand_read(1).);
|
||
FINSH_FUNCTION_EXPORT(nand_read2, nand_read(1).);
|
||
FINSH_FUNCTION_EXPORT(nand_read3, nand_read(1).);
|
||
FINSH_FUNCTION_EXPORT(nand_write, nand_write(1).);
|
||
FINSH_FUNCTION_EXPORT(nand_erase, nand_erase(100, 200). erase block in nand);
|