112 lines
4.5 KiB
C
112 lines
4.5 KiB
C
/************************************************************************/
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/* (C) Fujitsu Semiconductor Europe GmbH */
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/* */
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/* The following software deliverable is intended for and must only be */
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/* used for reference and in an evaluation laboratory environment. */
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/* It is provided on an as-is basis without charge and is subject to */
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/* alterations. */
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/* It is the user’s obligation to fully test the software in its */
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/* environment and to ensure proper functionality, qualification and */
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/* compliance with component specifications. */
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/* */
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/* In the event the software deliverable includes the use of open */
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/* source components, the provisions of the governing open source */
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/* license agreement shall apply with respect to such software */
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/* deliverable. */
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/* FSEU does not warrant that the deliverables do not infringe any */
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/* third party intellectual property right (IPR). In the event that */
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/* the deliverables infringe a third party IPR it is the sole */
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/* responsibility of the customer to obtain necessary licenses to */
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/* continue the usage of the deliverable. */
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/* */
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/* To the maximum extent permitted by applicable law FSEU disclaims all */
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/* warranties, whether express or implied, in particular, but not */
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/* limited to, warranties of merchantability and fitness for a */
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/* particular purpose for which the deliverable is not designated. */
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/* */
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/* To the maximum extent permitted by applicable law, FSEU's liability */
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/* is restricted to intention and gross negligence. */
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/* FSEU is not liable for consequential damages. */
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/* */
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/* (V1.4) */
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/************************************************************************/
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#include "mb9bf506r.h"
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/*
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* 80MHz : Master Clock
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*/
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const uint32_t SystemFrequency = 80000000UL;
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uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */
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uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */
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uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */
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uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */
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uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */
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/*
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* Prototype of internal function
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*/
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static void ClockInit(void);
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static void HwwdtDisable(void);
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/*
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* Setup the microcontroller system
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*/
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void SystemInit (void)
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{
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HwwdtDisable(); /* Disable Hardware Watchdog */
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ClockInit(); /* Initialize Clock */
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}
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/*
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* Initialize Clock
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*/
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static void ClockInit(void)
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{
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/*set Main clock stabilization
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wait time to 2ms*/
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FM3_CRG->CSW_TMR = 0x79;
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/*Enable Main Oscilator*/
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FM3_CRG->SCM_CTL |= 1<<1;
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/*Wait stabilization end*/
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while(!(FM3_CRG->SCM_STR & 0x02));
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/* sub CLK enable */
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//FM3_CRG->SCM_CTL |= 0x08;
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//while(!(FM3_CRG->SCM_STR & 0x08));
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/*Set PLL stabilization
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wait time to 512uS*/
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FM3_CRG->PSW_TMR |= 2;
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/*Set PLL to 80MHz*/
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FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/
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FM3_CRG->PLL_CTL2 = 19; /*N = 20*/
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/*Enable PLL*/
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FM3_CRG->SCM_CTL |= 0x10;
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/*Set bus prescalers*/
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FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/
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FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/
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FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/
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FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/
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/*Wait PLL stabilizatoin end*/
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while(!(FM3_CRG->SCM_STR & 0x10));
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/*Select PLL for main clock*/
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FM3_CRG->SCM_CTL |= 2<<5;
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/*Wait PLL to be connected*/
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while((FM3_CRG->SCM_STR & 0xe0) != 0x40);
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}
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/*
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* Stop HW Watchdog Timer
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*/
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static void HwwdtDisable(void)
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{
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/* UnLock (except WDG_CTL) */
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FM3_HWWDT->WDG_LCK = 0x1ACCE551;
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/* UnLock (WDG_CTL) */
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FM3_HWWDT->WDG_LCK = 0xE5331AAE;
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/* Disable WDG */
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FM3_HWWDT->WDG_CTL = 0x00;
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}
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