552 lines
19 KiB
Plaintext
552 lines
19 KiB
Plaintext
// -----------------------------------------------------------------------
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// This file contains the initial set up configuration for the AM335x.
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//-------------------------------------------------------------------------
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__var clk_in;
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CHGBIT (addr, mask, data)
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{
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__var reg;
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reg = __readMemory32(addr, "Memory");
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reg &= ~mask;
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reg |= data;
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__writeMemory32(reg, addr, "Memory");
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}
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CLRBIT (addr, mask)
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{
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__var reg;
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reg = __readMemory32(addr, "Memory");
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reg &= ~mask;
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__writeMemory32(reg, addr, "Memory");
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}
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SETBIT (addr, mask)
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{
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__var reg;
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reg = __readMemory32(addr, "Memory");
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reg |= mask;
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__writeMemory32(reg, addr, "Memory");
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}
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TESTBIT (addr, mask)
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{
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return(__readMemory32(addr, "Memory") & mask);
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}
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get_input_clock_frequency()
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{
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__var temp;
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temp = __readMemory32(((0x44E10000) + 0x40), "Memory");
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temp = temp >> 22;
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temp = temp & 0x3;
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if(temp == 0)
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{
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clk_in = 19; //19.2MHz
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__message "Input Clock Read from SYSBOOT[15:14]: 19.2MHz\n";
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}
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if(temp == 1)
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{
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clk_in = 24; //24MHz
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__message "Input Clock Read from SYSBOOT[15:14]: 24MHz\n";
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}
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if(temp == 2)
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{
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clk_in = 25; //25MHz
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__message "Input Clock Read from SYSBOOT[15:14]: 25MHz\n";
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}
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if(temp == 3)
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{
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clk_in = 26; //26MHz
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__message "Input Clock Read from SYSBOOT[15:14]: 26MHz\n";
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}
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}
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mpu_pll_config( clk_in, N, M, M2)
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{
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__var ref_clk,clk_out;
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__var clkmode,clksel,div_m2,idlest_dpll;
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__var temp,i;
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ref_clk = clk_in/(N+1);
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clk_out = (ref_clk*M)/M2;
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clkmode=__readMemory32((0x44E00000 + 0x488), "Memory");
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clksel= __readMemory32((0x44E00000 + 0x42C), "Memory");
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div_m2= __readMemory32((0x44E00000 + 0x4A8), "Memory");
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__message "**** Going to Bypass... \n";
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//put the DPLL in bypass mode
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__writeMemory32(0x4, (0x44E00000 + 0x488), "Memory");
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while(((__readMemory32((0x44E00000 + 0x420), "Memory") & 0x101) != 0x00000100)); //wait for bypass status
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__message "**** Bypassed, changing values... \n";
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//set multiply and divide values
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clksel = clksel & (~0x7FFFF);
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clksel = clksel | ((M <<0x8) | N);
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__writeMemory32(clksel, (0x44E00000 + 0x42C), "Memory");
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div_m2 = div_m2 & ~0x1F;
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div_m2 = div_m2 | M2;
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__writeMemory32(div_m2, (0x44E00000 + 0x4A8), "Memory");
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__message "**** Locking ARM PLL\n";
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//now lock the DPLL
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clkmode = clkmode | 0x7; //enables lock mode
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__writeMemory32(clkmode, (0x44E00000 + 0x488), "Memory");
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while(((__readMemory32((0x44E00000 + 0x420), "Memory") & 0x101) != 0x1)); //wait for lock
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}
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core_pll_config( clk_in, N, M, M4, M5, M6)
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{
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__var ref_clk,clk_out4,clk_out5,clk_out6;
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__var clkmode,clksel,div_m4,div_m5,div_m6,idlest_dpll;
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ref_clk = clk_in/(N+1);
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clk_out4 = (ref_clk*M)/M4; //M4=200MHz
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clk_out5 = (ref_clk*M)/M5; //M5=250MHz
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clk_out6 = (ref_clk*M)/M6; //M6=500MHz
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clkmode= __readMemory32((0x44E00000 + 0x490), "Memory");
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clksel= __readMemory32((0x44E00000 + 0x468), "Memory");
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div_m4= __readMemory32((0x44E00000 + 0x480), "Memory");
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div_m5= __readMemory32((0x44E00000 + 0x484), "Memory");
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div_m6= __readMemory32((0x44E00000 + 0x4D8), "Memory");
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//put DPLL in bypass mode
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clkmode = (clkmode & 0xfffffff8)|0x00000004;
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__writeMemory32(clkmode, (0x44E00000 + 0x490), "Memory");
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while((__readMemory32((0x44E00000 + 0x45C), "Memory") & 0x00000100 )!=0x00000100); //wait for bypass status
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__message "**** Core Bypassed\n";
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//set multiply and divide values
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clksel = clksel & (~0x7FFFF);
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clksel = clksel | ((M <<0x8) | N);
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__writeMemory32(clksel, (0x44E00000 + 0x468), "Memory");
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div_m4= M4; //200MHz
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__writeMemory32(div_m4, (0x44E00000 + 0x480), "Memory");
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div_m5= M5; //250MHz
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__writeMemory32(div_m5, (0x44E00000 + 0x484), "Memory");
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div_m6= M6; //500MHz
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__writeMemory32(div_m6, (0x44E00000 + 0x4D8), "Memory");
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__message "**** Now locking Core...\n";
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//now lock the PLL
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clkmode =(clkmode&0xfffffff8)|0x00000007;
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__writeMemory32(clkmode, (0x44E00000 + 0x490), "Memory");
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while((__readMemory32((0x44E00000 + 0x45C), "Memory") & 0x00000001 )!=0x00000001);
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__message "**** Core locked\n";
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}
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ddr_pll_config( clk_in, N, M, M2)
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{
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__var ref_clk,clk_out ;
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__var clkmode,clksel,div_m2,idlest_dpll;
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ref_clk = clk_in/(N+1);
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clk_out = (ref_clk*M)/M2;
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clkmode=__readMemory32((0x44E00000 + 0x494), "Memory");
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clksel= __readMemory32((0x44E00000 + 0x440), "Memory");
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div_m2= __readMemory32((0x44E00000 + 0x4A0), "Memory");
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clkmode =(clkmode&0xfffffff8)|0x00000004;
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__writeMemory32(clkmode, (0x44E00000 + 0x494), "Memory");
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while((__readMemory32((0x44E00000 + 0x434), "Memory") & 0x00000100 )!=0x00000100);
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__message "**** DDR DPLL Bypassed\n";
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clksel = clksel & (~0x7FFFF);
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clksel = clksel | ((M <<0x8) | N);
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__writeMemory32(clksel, (0x44E00000 + 0x440), "Memory");
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div_m2 = __readMemory32((0x44E00000 + 0x4A0), "Memory");
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div_m2 = (div_m2&0xFFFFFFE0) | M2;
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__writeMemory32(div_m2, (0x44E00000 + 0x4A0), "Memory");
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clkmode =(clkmode&0xfffffff8)|0x00000007;
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__writeMemory32(clkmode, (0x44E00000 + 0x494), "Memory");
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while((__readMemory32((0x44E00000 + 0x434), "Memory") & 0x00000001 )!=0x00000001);
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__message "**** DDR DPLL Locked\n";
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}
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per_pll_config( clk_in, N, M, M2)
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{
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__var ref_clk,clk_out;
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__var clkmode,clksel,div_m2,idlest_dpll;
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ref_clk = clk_in/(N+1);
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clk_out = (ref_clk*M)/M2;
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clkmode=__readMemory32((0x44E00000 + 0x48C), "Memory");
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clksel= __readMemory32((0x44E00000 + 0x49C), "Memory");
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div_m2= __readMemory32((0x44E00000 + 0x4AC), "Memory");
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clkmode =(clkmode&0xfffffff8)|0x00000004;
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__writeMemory32(clkmode, (0x44E00000 + 0x48C), "Memory");
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while((__readMemory32((0x44E00000 + 0x470), "Memory") & 0x00000100 )!=0x00000100);
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__message "**** PER DPLL Bypassed\n";
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clksel = clksel & (~0x7FFFF);
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clksel = clksel | ((M <<0x8) | N);
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__writeMemory32(clksel, (0x44E00000 + 0x49C), "Memory");
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div_m2= 0xFFFFFF80 | M2;
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__writeMemory32(div_m2, (0x44E00000 + 0x4AC), "Memory");
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clkmode =(clkmode&0xfffffff8)|0x00000007;
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__writeMemory32(clkmode,(0x44E00000 + 0x48C), "Memory");
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while((__readMemory32((0x44E00000 + 0x470), "Memory") & 0x00000001 )!=0x00000001);
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__message "**** PER DPLL Locked\n";
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}
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disp_pll_config( clk_in, N, M, M2)
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{
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__var ref_clk,clk_out;
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__var clkmode,clksel,div_m2,idlest_dpll;
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__message "**** DISP PLL Config is in progress .......... \n";
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ref_clk = clk_in/(N+1);
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clk_out = (ref_clk*M)/M2;
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clkmode=__readMemory32((0x44E00000 + 0x498), "Memory");
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clksel= __readMemory32((0x44E00000 + 0x454), "Memory");
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div_m2= __readMemory32((0x44E00000 + 0x4A4), "Memory");
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clkmode =(clkmode&0xfffffff8)|0x00000004;
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__writeMemory32(clkmode, (0x44E00000 + 0x498), "Memory");
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while((__readMemory32((0x44E00000 + 0x448), "Memory") & 0x00000100 )!=0x00000100);
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clksel = clksel & (~0x7FFFF);
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clksel = clksel | ((M <<0x8) | N);
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__writeMemory32(clksel, (0x44E00000 + 0x454), "Memory");
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div_m2= 0xFFFFFFE0 | M2;
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__writeMemory32(div_m2, (0x44E00000 + 0x4A4), "Memory");
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clkmode =(clkmode&0xfffffff8)|0x00000007;
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__writeMemory32(clkmode, (0x44E00000 + 0x498), "Memory");
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while((__readMemory32((0x44E00000 + 0x448), "Memory") & 0x00000001 )!=0x00000001);
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__message "**** DISP PLL Config is DONE .......... \n";
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}
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arm_opp120_config()
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{
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__message "**** Subarctic ALL ADPLL Config for OPP == OPP100 is In Progress ......... \n";
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get_input_clock_frequency();
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if (clk_in == 24)
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{
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mpu_pll_config(clk_in, 23, 550, 1);
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core_pll_config(clk_in, 23, 1000, 10, 8, 4);
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ddr_pll_config(clk_in, 23, 303, 1);
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per_pll_config(clk_in, 23, 960, 5);
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disp_pll_config(clk_in, 23, 48, 1);
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__message "**** Subarctic ALL ADPLL Config for OPP == OPP100 is Done ......... \n";
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}
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else
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{
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__message "**** Subarctic PLL Config failed!! Check SYSBOOT[15:14] for proper input freq config \n";
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}
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}
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emif_prcm_clk_enable()
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{
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__message "EMIF PRCM is in progress ....... \n";
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__writeMemory32(0x2, (0x44E00000 + 0x0D0), "Memory");
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__writeMemory32(0x2, (0x44E00000 + 0x028), "Memory");
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while(__readMemory32((0x44E00000 + 0x028), "Memory")!= 0x02);
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__message "EMIF PRCM Done \n";
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}
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vtp_enable()
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{
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/* Write 1 to enable VTP */
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__writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") | 0x00000040),((0x44E10000) + 0x0E0C) , "Memory");
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/* Write 0 to CLRZ bit */
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__writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") & 0xFFFFFFFE),((0x44E10000) + 0x0E0C) ,"Memory");
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/* Write 1 to CLRZ bit */
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__writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") | 0x00000001),((0x44E10000) + 0x0E0C) , "Memory");
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__message "Waiting for VTP Ready .......\n";
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while((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") & 0x00000020) != 0x00000020);
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__message "VTP Enable Done \n";
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}
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cmd_macro_config( REG_PHY_CTRL_SLAVE_RATIO_value, CMD_REG_PHY_CTRL_SLAVE_FORCE_value, CMD_REG_PHY_CTRL_SLAVE_DELAY_value, PHY_DLL_LOCK_DIFF_value, CMD_PHY_INVERT_CLKOUT_value)
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{
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__message "\DDR PHY CMD0 Register configuration is in progress ....... \n";
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__writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x01C + (0x44E12000)), "Memory");
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__writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x020 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x024 + (0x44E12000)), "Memory");
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__writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x028 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x02C + (0x44E12000)), "Memory");
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__message "\DDR PHY CMD1 Register configuration is in progress ....... \n";
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__writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x050 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x054 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x058 + (0x44E12000)), "Memory");
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__writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x05C + (0x44E12000)), "Memory");
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__writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x060 + (0x44E12000)), "Memory");
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__message "\DDR PHY CMD2 Register configuration is in progress ....... \n";
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__writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x084 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x088 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x08C + (0x44E12000)), "Memory");
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__writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x090 + (0x44E12000)), "Memory");
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__writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x094 + (0x44E12000)), "Memory");
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}
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data_macro_config( dataMacroNum, PHY_RD_DQS_SLAVE_RATIO_value, PHY_WR_DQS_SLAVE_RATIO_value, REG_PHY_WRLVL_INIT_RATIO_value,
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REG_PHY_GATELVL_INIT_RATIO_value, REG_PHY_FIFO_WE_SLAVE_RATIO_value, REG_PHY_WR_DATA_SLAVE_RATIO_value)
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{
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__var offset;
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if(dataMacroNum == 0)
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{
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offset = 0x00;
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__message "DDR PHY DATA0 Register configuration is in progress ....... \n";
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}
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else if(dataMacroNum == 1)
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{
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offset = 0xA4;
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__message "DDR PHY DATA1 Register configuration is in progress ....... \n";
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}
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__writeMemory32(((PHY_RD_DQS_SLAVE_RATIO_value<<30)|(PHY_RD_DQS_SLAVE_RATIO_value<<20)|(PHY_RD_DQS_SLAVE_RATIO_value<<10)|(PHY_RD_DQS_SLAVE_RATIO_value<<0)), ((0x0C8 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(PHY_RD_DQS_SLAVE_RATIO_value>>2, ((0x0CC + (0x44E12000)) + offset), "Memory");
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__writeMemory32(((PHY_WR_DQS_SLAVE_RATIO_value<<30)|(PHY_WR_DQS_SLAVE_RATIO_value<<20)|(PHY_WR_DQS_SLAVE_RATIO_value<<10)|(PHY_WR_DQS_SLAVE_RATIO_value<<0)), ((0x0DC + (0x44E12000)) + offset), "Memory");
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__writeMemory32(PHY_WR_DQS_SLAVE_RATIO_value>>2, ((0x0E0 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(((REG_PHY_WRLVL_INIT_RATIO_value<<30)|(REG_PHY_WRLVL_INIT_RATIO_value<<20)|(REG_PHY_WRLVL_INIT_RATIO_value<<10)|(REG_PHY_WRLVL_INIT_RATIO_value<<0)), ((0x0F0 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(REG_PHY_WRLVL_INIT_RATIO_value>>2, ((0x0F4 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(((REG_PHY_GATELVL_INIT_RATIO_value<<30)|(REG_PHY_GATELVL_INIT_RATIO_value<<20)|(REG_PHY_GATELVL_INIT_RATIO_value<<10)|(REG_PHY_GATELVL_INIT_RATIO_value<<0)), ((0x0FC + (0x44E12000)) + offset), "Memory");
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__writeMemory32(REG_PHY_GATELVL_INIT_RATIO_value>>2, ((0x100 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(((REG_PHY_FIFO_WE_SLAVE_RATIO_value<<30)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<20)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<10)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<0)), ((0x108 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(REG_PHY_FIFO_WE_SLAVE_RATIO_value>>2,((0x10C + (0x44E12000)) + offset), "Memory");
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__writeMemory32(((REG_PHY_WR_DATA_SLAVE_RATIO_value<<30)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<20)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<10)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<0)),((0x120 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(REG_PHY_WR_DATA_SLAVE_RATIO_value>>2, ((0x124 + (0x44E12000)) + offset), "Memory");
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__writeMemory32(0x0,((0x138 + (0x44E12000)) + offset), "Memory");
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}
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emif_mmr_config( Read_Latency, Timing1, Timing2, Timing3, Sdram_Config, Ref_Ctrl)
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{
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__var i;
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__message "emif Timing register configuration is in progress ....... \n";
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__writeMemory32(Read_Latency, (0x4C000000 + 0x0E4), "Memory");
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__writeMemory32(Read_Latency, (0x4C000000 + 0x0E8), "Memory");
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__writeMemory32(Read_Latency, (0x4C000000 + 0x0EC), "Memory");
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__writeMemory32(Timing1, (0x4C000000 + 0x018), "Memory");
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__writeMemory32(Timing1, (0x4C000000 + 0x01C), "Memory");
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__writeMemory32(Timing2, (0x4C000000 + 0x020), "Memory");
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__writeMemory32(Timing2, (0x4C000000 + 0x024), "Memory");
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__writeMemory32(Timing3, (0x4C000000 + 0x028), "Memory");
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__writeMemory32(Timing3, (0x4C000000 + 0x02C), "Memory");
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__writeMemory32(Sdram_Config, (0x4C000000 + 0x008), "Memory");
|
|
__writeMemory32(Sdram_Config, (0x4C000000 + 0x00C), "Memory");
|
|
__writeMemory32(0x00004650, (0x4C000000 + 0x010), "Memory");
|
|
__writeMemory32(0x00004650, (0x4C000000 + 0x014), "Memory");
|
|
|
|
for(i=0;i<5000;i++)
|
|
{
|
|
}
|
|
|
|
__writeMemory32(Ref_Ctrl, (0x4C000000 + 0x010), "Memory");
|
|
__writeMemory32(Ref_Ctrl, (0x4C000000 + 0x014), "Memory");
|
|
|
|
__writeMemory32(Sdram_Config, (0x4C000000 + 0x008), "Memory");
|
|
__writeMemory32(Sdram_Config, (0x4C000000 + 0x00C), "Memory");
|
|
|
|
__message "emif Timing register configuration is done ....... \n";
|
|
}
|
|
|
|
gpio_module_clk_config()
|
|
{
|
|
__var buff;
|
|
|
|
buff = __readMemory32((0x400 + 0x44E00000 + 0x8), "Memory");
|
|
|
|
buff |= 0x2;
|
|
|
|
__writeMemory32(buff, (0x400 + 0x44E00000 + 0x8), "Memory");
|
|
|
|
while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x3) != 0x2);
|
|
|
|
buff = __readMemory32((0x400 + 0x44E00000 + 0x8), "Memory");
|
|
|
|
buff |= 0x00040000;
|
|
|
|
__writeMemory32(buff, (0x400 + 0x44E00000 + 0x8), "Memory");
|
|
|
|
while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x00040000) != 0x00040000);
|
|
|
|
while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x00030000) != 0x0);
|
|
|
|
while((__readMemory32((0x400 + 0x44E00000), "Memory") & 0x00000100) != 0x00000100);
|
|
|
|
__message "GPIO module clock configuration is done ....... \n";
|
|
|
|
}
|
|
|
|
phy_config_cmd()
|
|
{
|
|
__var i;
|
|
|
|
for(i = 0; i < 3; i++)
|
|
{
|
|
__message "DDR PHY CMD Register configuration is in progress ....... \n";
|
|
|
|
__writeMemory32(0x40, ((0x44E12000 + 0x01c) + (i * 0x34)), "Memory");
|
|
|
|
__writeMemory32(0x1, ((0x44E12000 + 0x02c) + (i * 0x34)), "Memory");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
phy_config_data()
|
|
{
|
|
__var i;
|
|
|
|
for(i = 0; i < 2; i++)
|
|
{
|
|
__message "DDR PHY Data Register configuration is in progress ....... \n";
|
|
|
|
__writeMemory32(0x3B, ((0x44E12000 + 0x0c8) + (i * 0xA4)), "Memory");
|
|
|
|
__writeMemory32(0x85, ((0x44E12000 + 0x0DC) + (i * 0xA4)), "Memory");
|
|
|
|
__writeMemory32(0x100, ((0x44E12000 + 0x108) + (i * 0xA4)), "Memory");
|
|
|
|
__writeMemory32(0xC1, ((0x44E12000 + 0x120) + (i * 0xA4)), "Memory");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ddr3_emif_config()
|
|
{
|
|
__message "**** AM335x OPP120 DDR3 EMIF and PHY configuration is in progress......... \n";
|
|
|
|
emif_prcm_clk_enable();
|
|
|
|
__message "DDR PHY Configuration In progress \n";
|
|
|
|
/* Perform GPIO module clock configuration. */
|
|
gpio_module_clk_config();
|
|
|
|
__writeMemory32(0x00000067, (0x44E10000 + 0x964), "Memory");
|
|
|
|
__writeMemory32((__readMemory32((0x44E07000 + 0x130), "Memory") & 0xFFFFFFFE), (0x44E07000 + 0x130), "Memory");
|
|
|
|
__writeMemory32((__readMemory32((0x44E07000 + 0x10), "Memory") | 0x02), (0x44E07000 + 0x10), "Memory");
|
|
|
|
/* Wait until GPIO module is reset. */
|
|
|
|
while(!(__readMemory32((0x44E07000 + 0x114), "Memory") & 0x01));
|
|
|
|
__writeMemory32((__readMemory32((0x44E07000 + 0x134), "Memory") & ~(1 << 7)), (0x44E07000 + 0x134), "Memory");
|
|
|
|
__writeMemory32((1 << 7), (0x44E07000 + 0x194), "Memory");
|
|
|
|
__writeMemory32((__readMemory32((0x44E10000 + 0x0E0C), "Memory") & 0xFFFFFFFE), (0x44E10000 + 0x0E0C), "Memory");
|
|
|
|
__writeMemory32((__readMemory32((0x44E10000 + 0x0E0C), "Memory") | 0x00000001), (0x44E10000 + 0x0E0C), "Memory");
|
|
|
|
vtp_enable();
|
|
|
|
phy_config_cmd();
|
|
|
|
phy_config_data();
|
|
|
|
__writeMemory32(0x18B, (0x1404 + 0x44E10000), "Memory");
|
|
__writeMemory32(0x18B, (0x1408 + 0x44E10000), "Memory");
|
|
__writeMemory32(0x18B, (0x140C + 0x44E10000), "Memory");
|
|
__writeMemory32(0x18B, (0x1440 + 0x44E10000), "Memory");
|
|
__writeMemory32(0x18B, (0x1444 + 0x44E10000), "Memory");
|
|
|
|
__writeMemory32((__readMemory32((0x0E04 + 0x44E10000), "Memory") & ~0x10000000), (0x0E04 + 0x44E10000), "Memory");
|
|
|
|
__writeMemory32((__readMemory32((0x131C + 0x44E10000), "Memory") | 0x00000001), (0x131C + 0x44E10000), "Memory");
|
|
|
|
__message "EMIF Timing register configuration is in progress ....... \n";
|
|
|
|
__writeMemory32(0x06, (0x0E4 + 0x4C000000), "Memory");
|
|
__writeMemory32(0x06, (0x0E8 + 0x4C000000), "Memory");
|
|
__writeMemory32(0x06, (0x0EC + 0x4C000000), "Memory");
|
|
|
|
__writeMemory32(0x0888A39B, (0x018 + 0x4C000000), "Memory");
|
|
__writeMemory32(0x0888A39B, (0x01C + 0x4C000000), "Memory");
|
|
|
|
__writeMemory32(0x26337FDA, (0x020 + 0x4C000000), "Memory");
|
|
__writeMemory32(0x26337FDA, (0x024 + 0x4C000000), "Memory");
|
|
|
|
__writeMemory32(0x501F830F, (0x028 + 0x4C000000), "Memory");
|
|
__writeMemory32(0x501F830F, (0x02C + 0x4C000000), "Memory");
|
|
|
|
__writeMemory32(0x0000093B, (0x010 + 0x4C000000), "Memory");
|
|
__writeMemory32(0x0000093B, (0x014 + 0x4C000000), "Memory");
|
|
|
|
__writeMemory32(0x50074BE4, (0x0C8 + 0x4C000000), "Memory");
|
|
|
|
__writeMemory32(0x61C04AB2, (0x008 + 0x4C000000), "Memory");
|
|
|
|
__message "EMIF Timing register configuration is done ....... \n";
|
|
|
|
if((__readMemory32((0x4C000000 + 0x004), "Memory") & 0x4) == 0x4)
|
|
{
|
|
__message "PHY is READY!!\n";
|
|
}
|
|
|
|
__message "DDR PHY Configuration done \n";
|
|
|
|
__message "**** AM335x OPP120 DDR3 EMIF and PHY configuration is done......... \n";
|
|
}
|
|
|
|
am335x_evm_initialization()
|
|
{
|
|
__var psc_base;
|
|
__var reg;
|
|
__var module_offest;
|
|
|
|
__message " AM335x EVM-SK Initialization is in progress .......... \n";
|
|
arm_opp120_config();
|
|
ddr3_emif_config();
|
|
__message " AM335x EVM-SK Initialization is done .......... \n";
|
|
}
|
|
|
|
execUserPreload()
|
|
{
|
|
am335x_evm_initialization();
|
|
}
|
|
|