599 lines
17 KiB
C
599 lines
17 KiB
C
/*
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* x1000_dwc.h
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*
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* Created on: 2017Äê2ÔÂ3ÈÕ
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* Author: Urey
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*/
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#ifndef _X1000_DWC_H_
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#define _X1000_DWC_H_
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#define DWC_FORCE_SPEED_FULL 0
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#if DWC_FORCE_SPEED_FULL
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#define ENDPOINT_PACKET_SIZE 64
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#define CONTROL_MAX_PACKET_SIZE 64
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#else
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#define ENDPOINT_PACKET_SIZE 512
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#define CONTROL_MAX_PACKET_SIZE 64
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#endif
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#define DWC_EP_IN_OFS 0
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#define DWC_EP_OUT_OFS 16
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#define DWC_EPNO_MASK 0x7f
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typedef struct dwc_ep_t
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{
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uint8_t num; /* ep number used for register address lookup */
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#define EP_IDLE 0
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#define EP_TRANSFERED 1
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#define EP_TRANSFERING 2
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#define EP_SETUP 0
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#define EP_DATA 1
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#define EP_STATUS 2
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#define EP_SETUP_PHASEDONE 3
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uint32_t ep_state;
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uint32_t is_in; /* ep dir 1 = out */
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uint32_t active; /* ep active */
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uint32_t type; /* ep type */
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#define DWC_OTG_EP_TYPE_CONTROL 0
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#define DWC_OTG_EP_TYPE_ISOC 1
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#define DWC_OTG_EP_TYPE_BULK 2
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#define DWC_OTG_EP_TYPE_INTR 3
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uint32_t maxpacket; /* max packet bytes */
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// uint32_t ctrl_req_addr;
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void* xfer_buff; /* pointer to transfer buffer */
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uint32_t xfer_len; /* number of bytes to transfer */
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uint32_t xfer_count; /* number of bytes transfered */
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} dwc_ep;
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typedef union hwcfg1_data {
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uint32_t d32;
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struct {
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unsigned ep_dir0:2;
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unsigned ep_dir1:2;
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unsigned ep_dir2:2;
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unsigned ep_dir3:2;
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unsigned ep_dir4:2;
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unsigned ep_dir5:2;
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unsigned ep_dir6:2;
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unsigned ep_dir7:2;
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unsigned ep_dir8:2;
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unsigned ep_dir9:2;
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unsigned ep_dir10:2;
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unsigned ep_dir11:2;
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unsigned ep_dir12:2;
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unsigned ep_dir13:2;
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unsigned ep_dir14:2;
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unsigned ep_dir15:2;
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} b;
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#define DWC_HWCFG1_DIR_BIDIR 0x0
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#define DWC_HWCFG1_DIR_IN 0x1
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#define DWC_HWCFG1_DIR_OUT 0x2
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} hwcfg1_data_t;
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/**
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* This union represents the bit fields in the User HW Config2
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* Register. Read the register into the <i>d32</i> element then read
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* out the bits using the <i>b</i>it elements.
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*/
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typedef union hwcfg2_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/* GHWCFG2 */
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unsigned op_mode:3;
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#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
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#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
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#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
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#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
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#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
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#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
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#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
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unsigned architecture:2;
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unsigned point2point:1;
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unsigned hs_phy_type:2;
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#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
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#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
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#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
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#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
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unsigned fs_phy_type:2;
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unsigned num_dev_ep:4;
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unsigned num_host_chan:4;
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unsigned perio_ep_supported:1;
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unsigned dynamic_fifo:1;
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unsigned multi_proc_int:1;
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unsigned reserved21:1;
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unsigned nonperio_tx_q_depth:2;
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unsigned host_perio_tx_q_depth:2;
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unsigned dev_token_q_depth:5;
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unsigned otg_enable_ic_usb:1;
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} b;
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} hwcfg2_data_t;
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/**
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* This union represents the bit fields in the User HW Config3
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* Register. Read the register into the <i>d32</i> element then read
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* out the bits using the <i>b</i>it elements.
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*/
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typedef union hwcfg3_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/* GHWCFG3 */
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unsigned xfer_size_cntr_width:4;
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unsigned packet_size_cntr_width:3;
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unsigned otg_func:1;
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unsigned i2c:1;
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unsigned vendor_ctrl_if:1;
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unsigned optional_features:1;
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unsigned synch_reset_type:1;
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unsigned adp_supp:1;
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unsigned otg_enable_hsic:1;
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unsigned bc_support:1;
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unsigned otg_lpm_en:1;
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unsigned dfifo_depth:16;
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} b;
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} hwcfg3_data_t;
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/**
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* This union represents the bit fields in the User HW Config4
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* Register. Read the register into the <i>d32</i> element then read
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* out the bits using the <i>b</i>it elements.
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*/
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typedef union hwcfg4_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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unsigned num_dev_perio_in_ep:4;
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unsigned power_optimiz:1;
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unsigned min_ahb_freq:1;
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unsigned part_power_down:1;
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unsigned reserved:7;
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unsigned utmi_phy_data_width:2;
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unsigned num_dev_mode_ctrl_ep:4;
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unsigned iddig_filt_en:1;
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unsigned vbus_valid_filt_en:1;
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unsigned a_valid_filt_en:1;
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unsigned b_valid_filt_en:1;
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unsigned session_end_filt_en:1;
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unsigned ded_fifo_en:1;
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unsigned num_in_eps:4;
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unsigned desc_dma:1;
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unsigned desc_dma_dyn:1;
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} b;
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} hwcfg4_data_t;
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typedef union dwc_state {
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uint8_t d8;
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struct {
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unsigned event:1;
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#define USB_CABLE_DISCONNECT 0
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#define USB_CABLE_CONNECT 1
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#define USB_CABLE_SUSPEND 2
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#define USB_CONFIGURED 3
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unsigned state:7;
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}b;
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} dwc_st;
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typedef struct dwc_cfg_if_t
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{
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hwcfg1_data_t hwcfg1;
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hwcfg2_data_t hwcfg2;
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hwcfg3_data_t hwcfg3;
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hwcfg4_data_t hwcfg4;
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dwc_st status;
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#define USB_SPEED_HIGH 0
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#define USB_SPEED_FULL 1
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#define USB_SPEED_LOW 2
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uint8_t speed;
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uint8_t is_dma;
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// uint8_t ep0State;
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dwc_ep *dep[32];
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rt_sem_t isr_sem;
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} dwc_handle;
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/**
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* This union represents the bit fields in the Device Control
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* Register. Read the register into the <i>d32</i> member then
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* set/clear the bits using the <i>b</i>it elements.
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*/
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typedef union dctl_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/** Remote Wakeup */
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unsigned rmtwkupsig:1;
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/** Soft Disconnect */
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unsigned sftdiscon:1;
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/** Global Non-Periodic IN NAK Status */
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unsigned gnpinnaksts:1;
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/** Global OUT NAK Status */
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unsigned goutnaksts:1;
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/** Test Control */
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unsigned tstctl:3;
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/** Set Global Non-Periodic IN NAK */
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unsigned sgnpinnak:1;
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/** Clear Global Non-Periodic IN NAK */
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unsigned cgnpinnak:1;
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/** Set Global OUT NAK */
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unsigned sgoutnak:1;
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/** Clear Global OUT NAK */
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unsigned cgoutnak:1;
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/** Power-On Programming Done */
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unsigned pwronprgdone:1;
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/** Reserved */
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unsigned reserved:1;
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/** Global Multi Count */
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unsigned gmc:2;
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/** Ignore Frame Number for ISOC EPs */
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unsigned ifrmnum:1;
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/** NAK on Babble */
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unsigned nakonbble:1;
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/** Enable Continue on BNA */
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unsigned encontonbna:1;
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unsigned reserved18_31:14;
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} b;
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} dctl_data_t;
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/**
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* This union represents the bit fields of the Core Interrupt Mask
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* Register (GINTMSK). Set/clear the bits using the bit fields then
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* write the <i>d32</i> value to the register.
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*/
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typedef union gintmsk_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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unsigned reserved0:1;
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unsigned modemismatch:1;
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unsigned otgintr:1;
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unsigned sofintr:1;
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unsigned rxstsqlvl:1;
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unsigned nptxfempty:1;
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unsigned ginnakeff:1;
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unsigned goutnakeff:1;
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unsigned ulpickint:1;
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unsigned i2cintr:1;
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unsigned erlysuspend:1;
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unsigned usbsuspend:1;
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unsigned usbreset:1;
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unsigned enumdone:1;
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unsigned isooutdrop:1;
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unsigned eopframe:1;
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unsigned restoredone:1;
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unsigned epmismatch:1;
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unsigned inepintr:1;
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unsigned outepintr:1;
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unsigned incomplisoin:1;
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unsigned incomplisoout:1;
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unsigned fetsusp:1;
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unsigned resetdet:1;
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unsigned portintr:1;
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unsigned hcintr:1;
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unsigned ptxfempty:1;
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unsigned lpmtranrcvd:1;
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unsigned conidstschng:1;
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unsigned disconnect:1;
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unsigned sessreqintr:1;
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unsigned wkupintr:1;
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} b;
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} gintmsk_data_t;
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/**
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* This union represents the bit fields in the Device EP Control
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* Register. Read the register into the <i>d32</i> member then
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* set/clear the bits using the <i>b</i>it elements.
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*/
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typedef union depctl_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/** Maximum Packet Size
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* IN/OUT EPn
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* IN/OUT EP0 - 2 bits
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* 2'b00: 64 Bytes
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* 2'b01: 32
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* 2'b10: 16
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* 2'b11: 8 */
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unsigned mps:11;
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#define DWC_DEP0CTL_MPS_64 0
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#define DWC_DEP0CTL_MPS_32 1
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#define DWC_DEP0CTL_MPS_16 2
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#define DWC_DEP0CTL_MPS_8 3
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/** Next Endpoint
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* IN EPn/IN EP0
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* OUT EPn/OUT EP0 - reserved */
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unsigned nextep:4;
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/** USB Active Endpoint */
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unsigned usbactep:1;
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/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
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* This field contains the PID of the packet going to
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* be received or transmitted on this endpoint. The
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* application should program the PID of the first
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* packet going to be received or transmitted on this
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* endpoint , after the endpoint is
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* activated. Application use the SetD1PID and
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* SetD0PID fields of this register to program either
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* D0 or D1 PID.
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*
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* The encoding for this field is
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* - 0: D0
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* - 1: D1
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*/
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unsigned dpid:1;
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/** NAK Status */
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unsigned naksts:1;
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/** Endpoint Type
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* 2'b00: Control
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* 2'b01: Isochronous
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* 2'b10: Bulk
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* 2'b11: Interrupt */
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unsigned eptype:2;
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/** Snoop Mode
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* OUT EPn/OUT EP0
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* IN EPn/IN EP0 - reserved */
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unsigned snp:1;
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/** Stall Handshake */
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unsigned stall:1;
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/** Tx Fifo Number
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* IN EPn/IN EP0
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* OUT EPn/OUT EP0 - reserved */
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unsigned txfnum:4;
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/** Clear NAK */
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unsigned cnak:1;
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/** Set NAK */
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unsigned snak:1;
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/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
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* Writing to this field sets the Endpoint DPID (DPID)
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* field in this register to DATA0. Set Even
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* (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
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* Writing to this field sets the Even/Odd
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* (micro)frame (EO_FrNum) field to even (micro)
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* frame.
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*/
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unsigned setd0pid:1;
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/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
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* Writing to this field sets the Endpoint DPID (DPID)
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* field in this register to DATA1 Set Odd
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* (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
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* Writing to this field sets the Even/Odd
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* (micro)frame (EO_FrNum) field to odd (micro) frame.
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*/
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unsigned setd1pid:1;
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/** Endpoint Disable */
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unsigned epdis:1;
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/** Endpoint Enable */
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unsigned epena:1;
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} b;
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} depctl_data_t;
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/**
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* This union represents the bit fields in the Device IN EP Interrupt
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* Register and the Device IN EP Common Mask Register.
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*
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* - Read the register into the <i>d32</i> member then set/clear the
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* bits using the <i>b</i>it elements.
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*/
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typedef union diepint_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/** Transfer complete mask */
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unsigned xfercompl:1;
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/** Endpoint disable mask */
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unsigned epdisabled:1;
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/** AHB Error mask */
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unsigned ahberr:1;
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/** TimeOUT Handshake mask (non-ISOC EPs) */
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unsigned timeout:1;
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/** IN Token received with TxF Empty mask */
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unsigned intktxfemp:1;
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/** IN Token Received with EP mismatch mask */
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unsigned intknepmis:1;
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/** IN Endpoint NAK Effective mask */
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unsigned inepnakeff:1;
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/** Reserved */
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unsigned emptyintr:1;
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unsigned txfifoundrn:1;
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/** BNA Interrupt mask */
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unsigned bna:1;
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unsigned reserved10_12:3;
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/** BNA Interrupt mask */
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unsigned nak:1;
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unsigned reserved14_31:18;
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} b;
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} diepint_data_t;
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/**
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* This union represents the bit fields in the Device IN EP
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* Common/Dedicated Interrupt Mask Register.
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*/
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typedef union diepint_data diepmsk_data_t;
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/**
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* This union represents the bit fields in the Device OUT EP Interrupt
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* Registerand Device OUT EP Common Interrupt Mask Register.
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*
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* - Read the register into the <i>d32</i> member then set/clear the
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* bits using the <i>b</i>it elements.
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*/
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typedef union doepint_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/** Transfer complete */
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unsigned xfercompl:1;
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/** Endpoint disable */
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unsigned epdisabled:1;
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/** AHB Error */
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unsigned ahberr:1;
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/** Setup Phase Done (contorl EPs) */
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unsigned setup:1;
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/** OUT Token Received when Endpoint Disabled */
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unsigned outtknepdis:1;
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unsigned stsphsercvd:1;
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/** Back-to-Back SETUP Packets Received */
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unsigned back2backsetup:1;
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unsigned reserved7:1;
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/** OUT packet Error */
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unsigned outpkterr:1;
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/** BNA Interrupt */
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unsigned bna:1;
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unsigned reserved10:1;
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/** Packet Drop Status */
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unsigned pktdrpsts:1;
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/** Babble Interrupt */
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unsigned babble:1;
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/** NAK Interrupt */
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unsigned nak:1;
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/** NYET Interrupt */
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unsigned nyet:1;
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unsigned reserved15_31:17;
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} b;
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} doepint_data_t;
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/**
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* This union represents the bit fields in the Device OUT EP
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* Common/Dedicated Interrupt Mask Register.
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*/
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typedef union doepint_data doepmsk_data_t;
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/**
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* This union represents the bit fields in the Device All EP Interrupt
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* and Mask Registers.
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* - Read the register into the <i>d32</i> member then set/clear the
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* bits using the <i>b</i>it elements.
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*/
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typedef union daint_data {
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/** raw register data */
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uint32_t d32;
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/** register bits */
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struct {
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/** IN Endpoint bits */
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unsigned in:16;
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/** OUT Endpoint bits */
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unsigned out:16;
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} ep;
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struct {
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/** IN Endpoint bits */
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unsigned inep0:1;
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unsigned inep1:1;
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unsigned inep2:1;
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unsigned inep3:1;
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unsigned inep4:1;
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unsigned inep5:1;
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unsigned inep6:1;
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unsigned inep7:1;
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unsigned inep8:1;
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unsigned inep9:1;
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unsigned inep10:1;
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unsigned inep11:1;
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unsigned inep12:1;
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unsigned inep13:1;
|
|
unsigned inep14:1;
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|
unsigned inep15:1;
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|
/** OUT Endpoint bits */
|
|
unsigned outep0:1;
|
|
unsigned outep1:1;
|
|
unsigned outep2:1;
|
|
unsigned outep3:1;
|
|
unsigned outep4:1;
|
|
unsigned outep5:1;
|
|
unsigned outep6:1;
|
|
unsigned outep7:1;
|
|
unsigned outep8:1;
|
|
unsigned outep9:1;
|
|
unsigned outep10:1;
|
|
unsigned outep11:1;
|
|
unsigned outep12:1;
|
|
unsigned outep13:1;
|
|
unsigned outep14:1;
|
|
unsigned outep15:1;
|
|
} b;
|
|
} daint_data_t;
|
|
|
|
/*
|
|
* Functions
|
|
*/
|
|
/* USB Endpoint Callback Events */
|
|
#define USB_EVT_SETUP 1 /* Setup Packet */
|
|
#define USB_EVT_OUT 2 /* OUT Packet */
|
|
#define USB_EVT_IN 3 /* IN Packet */
|
|
#define USB_EVT_OUT_NAK 4 /* OUT Packet - Not Acknowledged */
|
|
#define USB_EVT_IN_NAK 5 /* IN Packet - Not Acknowledged */
|
|
#define USB_EVT_OUT_STALL 6 /* OUT Packet - Stalled */
|
|
#define USB_EVT_IN_STALL 7 /* IN Packet - Stalled */
|
|
#define USB_EVT_OUT_DMA_EOT 8 /* DMA OUT EP - End of Transfer */
|
|
#define USB_EVT_IN_DMA_EOT 9 /* DMA IN EP - End of Transfer */
|
|
#define USB_EVT_OUT_DMA_NDR 10 /* DMA OUT EP - New Descriptor Request */
|
|
#define USB_EVT_IN_DMA_NDR 11 /* DMA IN EP - New Descriptor Request */
|
|
#define USB_EVT_OUT_DMA_ERR 12 /* DMA OUT EP - Error */
|
|
#define USB_EVT_IN_DMA_ERR 13 /* DMA IN EP - Error */
|
|
#define USB_EVT_SOF 14
|
|
|
|
void x1000_usbd_init(dwc_handle *dwc);
|
|
void dwc_set_address(dwc_handle *dwc,uint8_t address);
|
|
int dwc_ep_disable(dwc_handle *dwc,uint8_t epnum);
|
|
int dwc_ep_enable(dwc_handle *dwc,uint8_t epnum);
|
|
|
|
int dwc_set_ep_stall(dwc_handle *dwc,uint8_t epnum);
|
|
int dwc_clr_ep_stall(dwc_handle *dwc,uint8_t epnum);
|
|
int dwc_enable_in_ep(dwc_handle *dwc,uint8_t epnum);
|
|
int dwc_enable_out_ep(dwc_handle *dwc,uint8_t epnum);
|
|
void dwc_ep0_status(dwc_handle *dwc);
|
|
void dwc_otg_ep0_out_start(dwc_handle *dwc);
|
|
|
|
void dwc_handle_ep_data_in_phase(dwc_handle *dwc, uint8_t epnum);
|
|
void dwc_handle_ep_status_in_phase(dwc_handle *dwc, uint8_t epnum);
|
|
void dwc_handle_ep_data_out_phase(dwc_handle *dwc,uint8_t epnum);
|
|
|
|
void dwc_ep_out_start(dwc_handle *dwc,uint8_t epnum);
|
|
int HW_GetPKT(dwc_handle *dwc, uint8_t epnum, uint8_t *buf,int size);
|
|
int HW_SendPKT(dwc_handle *dwc, uint8_t epnum, const uint8_t *buf, int size);
|
|
|
|
extern void x1000_usbd_event_cb(uint8_t epnum,uint32_t event,void *arg);
|
|
#endif /* _X1000_DWC_H_ */
|