1004 lines
34 KiB
C
1004 lines
34 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexio_spi.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
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enum _flexio_spi_transfer_states
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{
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kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */
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kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */
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};
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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extern const clock_ip_name_t s_flexioClocks[];
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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extern FLEXIO_Type *const s_flexioBases[];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
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/*!
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* @brief Send a piece of data for SPI.
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*
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* This function computes the number of data to be written into D register or Tx FIFO,
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* and write the data into it. At the same time, this function updates the values in
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* master handle structure.
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*
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* @param base pointer to FLEXIO_SPI_Type structure
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* @param handle Pointer to SPI master handle structure.
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*/
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static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
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/*!
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* @brief Receive a piece of data for SPI master.
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*
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* This function computes the number of data to receive from D register or Rx FIFO,
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* and write the data to destination address. At the same time, this function updates
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* the values in master handle structure.
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*
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* @param base pointer to FLEXIO_SPI_Type structure
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* @param handle Pointer to SPI master handle structure.
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*/
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static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Codes
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******************************************************************************/
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uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
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{
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return FLEXIO_GetInstance(base->flexioBase);
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}
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static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
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{
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uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
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if (handle->txData != NULL)
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{
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/* Transmit data and update tx size/buff. */
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if (handle->bytePerFrame == 1U)
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{
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tmpData = *(handle->txData);
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handle->txData++;
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}
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else
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{
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if (handle->direction == kFLEXIO_SPI_MsbFirst)
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{
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tmpData = (uint32_t)(handle->txData[0]) << 8U;
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tmpData += handle->txData[1];
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}
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else
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{
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tmpData = (uint32_t)(handle->txData[1]) << 8U;
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tmpData += handle->txData[0];
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}
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handle->txData += 2U;
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}
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}
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else
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{
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tmpData = FLEXIO_SPI_DUMMYDATA;
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}
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handle->txRemainingBytes -= handle->bytePerFrame;
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FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
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if (!handle->txRemainingBytes)
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{
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FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
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}
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}
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static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
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{
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uint16_t tmpData;
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tmpData = FLEXIO_SPI_ReadData(base, handle->direction);
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if (handle->rxData != NULL)
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{
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if (handle->bytePerFrame == 1U)
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{
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*handle->rxData = tmpData;
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handle->rxData++;
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}
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else
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{
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if (handle->direction == kFLEXIO_SPI_MsbFirst)
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{
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*((uint16_t *)(handle->rxData)) = tmpData;
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}
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else
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{
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*((uint16_t *)(handle->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU));
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}
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handle->rxData += 2U;
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}
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}
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handle->rxRemainingBytes -= handle->bytePerFrame;
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}
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void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
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{
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assert(base);
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assert(masterConfig);
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t ctrlReg = 0;
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uint16_t timerDiv = 0;
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uint16_t timerCmp = 0;
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/* Clear the shifterConfig & timerConfig struct. */
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memset(&shifterConfig, 0, sizeof(shifterConfig));
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memset(&timerConfig, 0, sizeof(timerConfig));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure FLEXIO SPI Master */
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ctrlReg = base->flexioBase->CTRL;
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ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
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ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
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FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
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if (!masterConfig->enableInDoze)
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{
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ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
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}
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base->flexioBase->CTRL = ctrlReg;
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/* Do hardware configuration. */
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/* 1. Configure the shifter 0 for tx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
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shifterConfig.pinSelect = base->SDOPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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}
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else
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
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/* 2. Configure the shifter 1 for rx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinSelect = base->SDIPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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}
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else
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
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/*3. Configure the timer 0 for SCK. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinSelect = base->SCKPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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timerDiv = srcClock_Hz / masterConfig->baudRate_Bps;
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timerDiv = timerDiv / 2 - 1;
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timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U;
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timerCmp |= timerDiv;
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timerConfig.timerCompare = timerCmp;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
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/* 4. Configure the timer 1 for CSn. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinSelect = base->CSnPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
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timerConfig.timerCompare = 0xFFFFU;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
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}
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void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
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{
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base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
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base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
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base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
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base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
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base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
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base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
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base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
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}
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void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
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{
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assert(masterConfig);
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masterConfig->enableMaster = true;
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masterConfig->enableInDoze = false;
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masterConfig->enableInDebug = true;
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masterConfig->enableFastAccess = false;
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/* Default baud rate 500kbps. */
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masterConfig->baudRate_Bps = 500000U;
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/* Default CPHA = 0. */
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masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
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/* Default bit count at 8. */
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masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
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}
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void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
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{
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assert(base && slaveConfig);
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t ctrlReg = 0;
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/* Clear the shifterConfig & timerConfig struct. */
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memset(&shifterConfig, 0, sizeof(shifterConfig));
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memset(&timerConfig, 0, sizeof(timerConfig));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure FLEXIO SPI Slave */
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ctrlReg = base->flexioBase->CTRL;
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ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
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ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) |
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FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave));
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if (!slaveConfig->enableInDoze)
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{
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ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
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}
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base->flexioBase->CTRL = ctrlReg;
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/* Do hardware configuration. */
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/* 1. Configure the shifter 0 for tx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
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shifterConfig.pinSelect = base->SDOPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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}
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else
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
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/* 2. Configure the shifter 1 for rx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinSelect = base->SDIPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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}
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else
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
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/*3. Configure the timer 0 for shift clock. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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timerConfig.pinSelect = base->SCKPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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/* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous
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PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
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}
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else
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{
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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}
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timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
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}
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void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
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{
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FLEXIO_SPI_MasterDeinit(base);
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}
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void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
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{
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assert(slaveConfig);
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slaveConfig->enableSlave = true;
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slaveConfig->enableInDoze = false;
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slaveConfig->enableInDebug = true;
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slaveConfig->enableFastAccess = false;
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/* Default CPHA = 0. */
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slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
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/* Default bit count at 8. */
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slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
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}
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void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
|
|
{
|
|
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]);
|
|
}
|
|
if (mask & kFLEXIO_SPI_RxFullInterruptEnable)
|
|
{
|
|
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable)
|
|
{
|
|
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]);
|
|
}
|
|
if (mask & kFLEXIO_SPI_RxFullInterruptEnable)
|
|
{
|
|
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
|
|
{
|
|
if (mask & kFLEXIO_SPI_TxDmaEnable)
|
|
{
|
|
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable);
|
|
}
|
|
|
|
if (mask & kFLEXIO_SPI_RxDmaEnable)
|
|
{
|
|
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable);
|
|
}
|
|
}
|
|
|
|
uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
|
|
{
|
|
uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
|
|
uint32_t status = 0;
|
|
|
|
status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
|
|
status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
|
|
|
|
return status;
|
|
}
|
|
|
|
void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kFLEXIO_SPI_TxBufferEmptyFlag)
|
|
{
|
|
FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
|
|
}
|
|
if (mask & kFLEXIO_SPI_RxBufferFullFlag)
|
|
{
|
|
FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
|
|
{
|
|
uint16_t timerDiv = 0;
|
|
uint16_t timerCmp = 0;
|
|
FLEXIO_Type *flexioBase = base->flexioBase;
|
|
|
|
/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
|
|
timerDiv = srcClockHz / baudRate_Bps;
|
|
timerDiv = timerDiv / 2 - 1U;
|
|
|
|
timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
|
|
timerCmp &= 0xFF00U;
|
|
timerCmp |= timerDiv;
|
|
|
|
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
|
|
}
|
|
|
|
void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_shift_direction_t direction,
|
|
const uint8_t *buffer,
|
|
size_t size)
|
|
{
|
|
assert(buffer);
|
|
assert(size);
|
|
|
|
while (size--)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag))
|
|
{
|
|
}
|
|
FLEXIO_SPI_WriteData(base, direction, *buffer++);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_shift_direction_t direction,
|
|
uint8_t *buffer,
|
|
size_t size)
|
|
{
|
|
assert(buffer);
|
|
assert(size);
|
|
|
|
while (size--)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag))
|
|
{
|
|
}
|
|
*buffer++ = FLEXIO_SPI_ReadData(base, direction);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
|
|
{
|
|
flexio_spi_shift_direction_t direction;
|
|
uint8_t bytesPerFrame;
|
|
uint32_t dataMode = 0;
|
|
uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
|
|
uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
|
|
timerCmp &= 0x00FFU;
|
|
/* Configure the values in handle. */
|
|
switch (xfer->flags)
|
|
{
|
|
case kFLEXIO_SPI_8bitMsb:
|
|
dataMode = (8 * 2 - 1U) << 8U;
|
|
bytesPerFrame = 1;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
|
|
case kFLEXIO_SPI_8bitLsb:
|
|
dataMode = (8 * 2 - 1U) << 8U;
|
|
bytesPerFrame = 1;
|
|
direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
|
|
case kFLEXIO_SPI_16bitMsb:
|
|
dataMode = (16 * 2 - 1U) << 8U;
|
|
bytesPerFrame = 2;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
|
|
case kFLEXIO_SPI_16bitLsb:
|
|
dataMode = (16 * 2 - 1U) << 8U;
|
|
bytesPerFrame = 2;
|
|
direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
|
|
default:
|
|
dataMode = (8 * 2 - 1U) << 8U;
|
|
bytesPerFrame = 1;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
assert(true);
|
|
break;
|
|
}
|
|
|
|
dataMode |= timerCmp;
|
|
|
|
/* Configure transfer size. */
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
|
|
|
while (xfer->dataSize)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag))
|
|
{
|
|
}
|
|
if (xfer->txData != NULL)
|
|
{
|
|
/* Transmit data and update tx size/buff. */
|
|
if (bytesPerFrame == 1U)
|
|
{
|
|
tmpData = *(xfer->txData);
|
|
xfer->txData++;
|
|
}
|
|
else
|
|
{
|
|
if (direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
tmpData = (uint32_t)(xfer->txData[0]) << 8U;
|
|
tmpData += xfer->txData[1];
|
|
}
|
|
else
|
|
{
|
|
tmpData = (uint32_t)(xfer->txData[1]) << 8U;
|
|
tmpData += xfer->txData[0];
|
|
}
|
|
xfer->txData += 2U;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
}
|
|
|
|
xfer->dataSize -= bytesPerFrame;
|
|
|
|
FLEXIO_SPI_WriteData(base, direction, tmpData);
|
|
|
|
while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag))
|
|
{
|
|
}
|
|
tmpData = FLEXIO_SPI_ReadData(base, direction);
|
|
|
|
if (xfer->rxData != NULL)
|
|
{
|
|
if (bytesPerFrame == 1U)
|
|
{
|
|
*xfer->rxData = tmpData;
|
|
xfer->rxData++;
|
|
}
|
|
else
|
|
{
|
|
if (direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
*((uint16_t *)(xfer->rxData)) = tmpData;
|
|
}
|
|
else
|
|
{
|
|
*((uint16_t *)(xfer->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU));
|
|
}
|
|
xfer->rxData += 2U;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
|
|
flexio_spi_master_handle_t *handle,
|
|
flexio_spi_master_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
|
|
|
|
/* Zero the handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Register callback and userData. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Enable interrupt in NVIC. */
|
|
EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
|
|
}
|
|
|
|
status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_master_handle_t *handle,
|
|
flexio_spi_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
|
|
uint32_t dataMode = 0;
|
|
uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]];
|
|
uint16_t tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
|
|
timerCmp &= 0x00FFU;
|
|
|
|
/* Check if SPI is busy. */
|
|
if (handle->state == kFLEXIO_SPI_Busy)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Busy;
|
|
}
|
|
|
|
/* Check if the argument is legal. */
|
|
if ((xfer->txData == NULL) && (xfer->rxData == NULL))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Configure the values in handle */
|
|
switch (xfer->flags)
|
|
{
|
|
case kFLEXIO_SPI_8bitMsb:
|
|
dataMode = (8 * 2 - 1U) << 8U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case kFLEXIO_SPI_8bitLsb:
|
|
dataMode = (8 * 2 - 1U) << 8U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
case kFLEXIO_SPI_16bitMsb:
|
|
dataMode = (16 * 2 - 1U) << 8U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case kFLEXIO_SPI_16bitLsb:
|
|
dataMode = (16 * 2 - 1U) << 8U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
default:
|
|
dataMode = (8 * 2 - 1U) << 8U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
assert(true);
|
|
break;
|
|
}
|
|
|
|
dataMode |= timerCmp;
|
|
|
|
/* Configure transfer size. */
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
|
|
|
handle->state = kFLEXIO_SPI_Busy;
|
|
handle->txData = xfer->txData;
|
|
handle->rxData = xfer->rxData;
|
|
handle->rxRemainingBytes = xfer->dataSize;
|
|
|
|
/* Save total transfer size. */
|
|
handle->transferSize = xfer->dataSize;
|
|
|
|
/* Send first byte of data to trigger the rx interrupt. */
|
|
if (handle->txData != NULL)
|
|
{
|
|
/* Transmit data and update tx size/buff. */
|
|
if (handle->bytePerFrame == 1U)
|
|
{
|
|
tmpData = *(handle->txData);
|
|
handle->txData++;
|
|
}
|
|
else
|
|
{
|
|
if (handle->direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
tmpData = (uint32_t)(handle->txData[0]) << 8U;
|
|
tmpData += handle->txData[1];
|
|
}
|
|
else
|
|
{
|
|
tmpData = (uint32_t)(handle->txData[1]) << 8U;
|
|
tmpData += handle->txData[0];
|
|
}
|
|
handle->txData += 2U;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
}
|
|
|
|
handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame;
|
|
|
|
FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
|
|
|
|
/* Enable transmit and receive interrupt to handle rx. */
|
|
FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Return remaing bytes in different cases. */
|
|
if (handle->rxData)
|
|
{
|
|
*count = handle->transferSize - handle->rxRemainingBytes;
|
|
}
|
|
else
|
|
{
|
|
*count = handle->transferSize - handle->txRemainingBytes;
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
|
|
FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
|
|
|
|
/* Transfer finished, set the state to idle. */
|
|
handle->state = kFLEXIO_SPI_Idle;
|
|
|
|
/* Clear the internal state. */
|
|
handle->rxRemainingBytes = 0;
|
|
handle->txRemainingBytes = 0;
|
|
}
|
|
|
|
void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
|
|
{
|
|
assert(spiHandle);
|
|
|
|
flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
|
|
FLEXIO_SPI_Type *base;
|
|
uint32_t status;
|
|
|
|
if (handle->state == kFLEXIO_SPI_Idle)
|
|
{
|
|
return;
|
|
}
|
|
|
|
base = (FLEXIO_SPI_Type *)spiType;
|
|
status = FLEXIO_SPI_GetStatusFlags(base);
|
|
|
|
/* Handle rx. */
|
|
if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes))
|
|
{
|
|
FLEXIO_SPI_TransferReceiveTransaction(base, handle);
|
|
}
|
|
|
|
/* Handle tx. */
|
|
if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes))
|
|
{
|
|
FLEXIO_SPI_TransferSendTransaction(base, handle);
|
|
}
|
|
|
|
/* All the transfer finished. */
|
|
if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
|
|
{
|
|
FLEXIO_SPI_MasterTransferAbort(base, handle);
|
|
if (handle->callback)
|
|
{
|
|
(handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
|
|
flexio_spi_slave_handle_t *handle,
|
|
flexio_spi_slave_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
|
|
|
|
/* Zero the handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Register callback and userData. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Enable interrupt in NVIC. */
|
|
EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
|
|
}
|
|
|
|
status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_slave_handle_t *handle,
|
|
flexio_spi_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
|
|
uint32_t dataMode = 0;
|
|
|
|
/* Check if SPI is busy. */
|
|
if (handle->state == kFLEXIO_SPI_Busy)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Busy;
|
|
}
|
|
|
|
/* Check if the argument is legal. */
|
|
if ((xfer->txData == NULL) && (xfer->rxData == NULL))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Configure the values in handle */
|
|
switch (xfer->flags)
|
|
{
|
|
case kFLEXIO_SPI_8bitMsb:
|
|
dataMode = 8 * 2 - 1U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case kFLEXIO_SPI_8bitLsb:
|
|
dataMode = 8 * 2 - 1U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
case kFLEXIO_SPI_16bitMsb:
|
|
dataMode = 16 * 2 - 1U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case kFLEXIO_SPI_16bitLsb:
|
|
dataMode = 16 * 2 - 1U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
default:
|
|
dataMode = 8 * 2 - 1U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
assert(true);
|
|
break;
|
|
}
|
|
|
|
/* Configure transfer size. */
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
|
|
|
handle->state = kFLEXIO_SPI_Busy;
|
|
handle->txData = xfer->txData;
|
|
handle->rxData = xfer->rxData;
|
|
handle->txRemainingBytes = xfer->dataSize;
|
|
handle->rxRemainingBytes = xfer->dataSize;
|
|
|
|
/* Save total transfer size. */
|
|
handle->transferSize = xfer->dataSize;
|
|
|
|
/* Enable transmit and receive interrupt to handle tx and rx. */
|
|
FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable);
|
|
FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
|
|
{
|
|
assert(spiHandle);
|
|
|
|
flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
|
|
FLEXIO_SPI_Type *base;
|
|
uint32_t status;
|
|
|
|
if (handle->state == kFLEXIO_SPI_Idle)
|
|
{
|
|
return;
|
|
}
|
|
|
|
base = (FLEXIO_SPI_Type *)spiType;
|
|
status = FLEXIO_SPI_GetStatusFlags(base);
|
|
|
|
/* Handle tx. */
|
|
if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes))
|
|
{
|
|
FLEXIO_SPI_TransferSendTransaction(base, handle);
|
|
}
|
|
|
|
/* Handle rx. */
|
|
if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes))
|
|
{
|
|
FLEXIO_SPI_TransferReceiveTransaction(base, handle);
|
|
}
|
|
|
|
/* All the transfer finished. */
|
|
if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
|
|
{
|
|
FLEXIO_SPI_SlaveTransferAbort(base, handle);
|
|
if (handle->callback)
|
|
{
|
|
(handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
|
|
}
|
|
}
|
|
}
|