576 lines
16 KiB
C
576 lines
16 KiB
C
#include <rthw.h>
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#include <rtthread.h>
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#include "stm32f10x.h"
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#include "codec.h"
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#define CODEC_MASTER_MODE 0
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/*
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SCLK PA5 SPI1_SCK
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SDIN PA7 SPI1_MOSI
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CSB PC5
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*/
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#define CODEC_CSB_PORT GPIOC
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#define CODEC_CSB_PIN GPIO_Pin_5
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#define codec_set_csb() do { CODEC_CSB_PORT->BSRR = CODEC_CSB_PIN; } while (0)
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#define codec_reset_csb() do { CODEC_CSB_PORT->BRR = CODEC_CSB_PIN; } while (0)
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void vol(uint16_t v);
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static void codec_send(rt_uint16_t s_data);
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#define DATA_NODE_MAX 5
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/* data node for Tx Mode */
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struct codec_data_node
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{
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rt_uint16_t *data_ptr;
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rt_size_t data_size;
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};
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struct codec_device
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{
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/* inherit from rt_device */
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struct rt_device parent;
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/* pcm data list */
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struct codec_data_node data_list[DATA_NODE_MAX];
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rt_uint16_t read_index, put_index;
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/* transmitted offset of current data node */
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rt_size_t offset;
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};
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struct codec_device codec;
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static uint16_t r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8;
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static uint16_t zero = 0;
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static void NVIC_Configuration(void)
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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/* SPI2 IRQ Channel configuration */
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NVIC_InitStructure.NVIC_IRQChannel = SPI2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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/* DMA1 IRQ Channel configuration */
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NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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}
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static void GPIO_Configuration(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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/* Disable the JTAG interface and enable the SWJ interface */
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GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
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/* PC5 CODEC CS */
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GPIO_InitStructure.GPIO_Pin = CODEC_CSB_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_Init(CODEC_CSB_PORT, &GPIO_InitStructure);
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#if CODEC_MASTER_MODE
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// WS, CK
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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// SD
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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#else
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/* Configure SPI2 pins: CK, WS and SD */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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#endif
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#ifdef CODEC_USE_MCO
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/* MCO configure */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_Init(GPIOA,&GPIO_InitStructure);
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RCC_MCOConfig(RCC_MCO_HSE);
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#endif
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}
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static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
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{
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DMA_InitTypeDef DMA_InitStructure;
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/* DMA1 Channel2 configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel5, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI2->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) addr;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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#if CODEC_MASTER_MODE
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while ((SPI2->SR & SPI_SR_CHSIDE) == 1);
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DMA_ClearFlag(DMA1_FLAG_TC5);
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#endif
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DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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/* Enable SPI2 DMA Tx request */
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SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
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DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
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DMA_Cmd(DMA1_Channel5, ENABLE);
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}
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#if CODEC_MASTER_MODE
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static void DMA_ZeroFill_I2S()
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{
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DMA_InitTypeDef DMA_InitStructure;
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/* DMA1 Channel2 configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel5, DISABLE);
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DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI2->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) &zero;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = 1;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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/* Enable SPI2 DMA Tx request */
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SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
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//DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
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DMA_Cmd(DMA1_Channel5, ENABLE);
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}
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#endif
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static void I2S_Configuration(void)
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{
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I2S_InitTypeDef I2S_InitStructure;
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/* I2S peripheral configuration */
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I2S_InitStructure.I2S_Standard = I2S_Standard_Phillips;
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I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
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I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
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I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_44k;
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I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
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/* I2S2 configuration */
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#if CODEC_MASTER_MODE
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I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveTx;
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#else
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I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
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#endif
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I2S_Init(SPI2, &I2S_InitStructure);
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}
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uint8_t SPI_WriteByte(unsigned char data)
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{
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//Wait until the transmit buffer is empty
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while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET);
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// Send the byte
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SPI_I2S_SendData(SPI1, data);
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//Wait until a data is received
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while (SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_RXNE) == RESET);
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// Get the received data
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data = SPI_I2S_ReceiveData(SPI1);
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// Return the shifted data
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return data;
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}
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static void codec_send(rt_uint16_t s_data)
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{
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codec_reset_csb();
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SPI_WriteByte((s_data >> 8) & 0xFF);
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SPI_WriteByte(s_data & 0xFF);
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codec_set_csb();
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}
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static rt_err_t codec_init(rt_device_t dev)
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{
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codec_send(REG_SOFTWARE_RESET);
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// 1.5x boost power up sequence.
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// Mute all outputs.
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codec_send(REG_LOUT1_VOL | LOUT1MUTE);
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codec_send(REG_ROUT1_VOL | ROUT1MUTE);
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codec_send(REG_LOUT2_VOL | LOUT2MUTE);
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codec_send(REG_ROUT2_VOL | ROUT2MUTE);
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// Enable unused output chosen from L/ROUT2, OUT3 or OUT4.
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codec_send(REG_POWER_MANAGEMENT3 | OUT4EN);
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// Set BUFDCOPEN=1 and BUFIOEN=1 in register R1
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN);
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// Set SPKBOOST=1 in register R49.
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codec_send(REG_OUTPUT | SPKBOOST);
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// Set VMIDSEL[1:0] to required value in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K);
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// Set L/RMIXEN=1 and DACENL/R=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR);
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// Set BIASEN=1 in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN);
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// Set L/ROUT2EN=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR | LOUT2EN | ROUT2EN);
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// Enable other mixers as required.
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// Enable other outputs as required.
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codec_send(REG_POWER_MANAGEMENT2 | LOUT1EN | ROUT1EN | BOOSTENL | BOOSTENR | INPPGAENL | INPPGAENR);
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// Digital inferface setup.
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codec_send(REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S);
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// PLL setup.
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// fs = 44.1KHz / 256fs = 11.2896MHz
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// F_PLL = 11.2896MHz * 4 * 2 = 90.3168MHz
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// R = 90.3168MHz / 12.288MHz = 7.35
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// PLL_N = 7
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// PLL_K = 5872026 (5921370 for STM32's 44.117KHz fs generated from 72MHz clock)
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codec_send(REG_PLL_N | 7);
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0x12D);
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codec_send(REG_PLL_K3 | 0x5A);
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN | PLLEN);
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codec_send(r06);
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// Enable DAC 128x oversampling.
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codec_send(REG_DAC | DACOSR128);
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// Set LOUT2/ROUT2 in BTL operation.
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codec_send(REG_BEEP | INVROUT2);
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// Set output volume to -22dB.
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vol(20);
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return RT_EOK;
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}
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// Exported functions
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#include <finsh.h>
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void vol(uint16_t v)
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{
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v = (v & VOL_MASK) << VOL_POS;
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codec_send(REG_LOUT1_VOL | v);
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codec_send(REG_ROUT1_VOL | HPVU | v);
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codec_send(REG_LOUT2_VOL | v);
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codec_send(REG_ROUT2_VOL | SPKVU | v);
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}
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void eq1(uint8_t freq, uint8_t gain, uint8_t mode)
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{
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codec_send(REG_EQ1 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (mode ? EQ3DMODE_DAC : EQ3DMODE_ADC));
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}
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void eq2(uint8_t freq, uint8_t gain, uint8_t bw)
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{
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codec_send(REG_EQ2 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ2BW_WIDE : EQ2BW_NARROW));
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}
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void eq3(uint8_t freq, uint8_t gain, uint8_t bw)
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{
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codec_send(REG_EQ3 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ3BW_WIDE : EQ3BW_NARROW));
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}
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void eq4(uint8_t freq, uint8_t gain, uint8_t bw)
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{
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codec_send(REG_EQ4 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS) | (bw ? EQ4BW_WIDE : EQ4BW_NARROW));
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}
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void eq5(uint8_t freq, uint8_t gain)
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{
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codec_send(REG_EQ2 | ((freq & EQC_MASK) << EQC_POS) | ((gain & EQG_MASK) << EQG_POS));
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}
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void eq3d(uint8_t depth)
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{
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codec_send(REG_3D | ((depth & DEPTH3D_MASK) << DEPTH3D_POS));
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}
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void sample_rate(uint8_t sr)
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{
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if (sr == 44)
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{
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codec_send(REG_ADDITIONAL | SR_48KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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codec_send(r06);
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}
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else
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{
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switch (sr)
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{
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case 8:
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codec_send(REG_ADDITIONAL | SR_8KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV6 | BCLK_DIV8 | (r06 & MS);
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break;
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case 12:
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codec_send(REG_ADDITIONAL | SR_12KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
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break;
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case 16:
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codec_send(REG_ADDITIONAL | SR_16KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV3 | BCLK_DIV8 | (r06 & MS);
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break;
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case 24:
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codec_send(REG_ADDITIONAL | SR_24KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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break;
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case 32:
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codec_send(REG_ADDITIONAL | SR_32KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1_5 | BCLK_DIV8 | (r06 & MS);
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break;
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case 48:
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codec_send(REG_ADDITIONAL | SR_48KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1 | BCLK_DIV8 | (r06 & MS);
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break;
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default:
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return;
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}
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codec_send(r06);
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}
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}
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FINSH_FUNCTION_EXPORT(vol, Set volume);
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FINSH_FUNCTION_EXPORT(eq1, Set EQ1(Cut-off, Gain, Mode));
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FINSH_FUNCTION_EXPORT(eq2, Set EQ2(Center, Gain, Bandwidth));
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FINSH_FUNCTION_EXPORT(eq3, Set EQ3(Center, Gain, Bandwidth));
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FINSH_FUNCTION_EXPORT(eq4, Set EQ4(Center, Gain, Bandwidth));
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FINSH_FUNCTION_EXPORT(eq5, Set EQ5(Cut-off, Gain));
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FINSH_FUNCTION_EXPORT(eq3d, Set 3D(Depth));
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FINSH_FUNCTION_EXPORT(sample_rate, Set sample rate);
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static rt_err_t codec_open(rt_device_t dev, rt_uint16_t oflag)
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{
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/* enable I2S */
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I2S_Cmd(SPI2, ENABLE);
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#if CODEC_MASTER_MODE
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DMA_ZeroFill_I2S();
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r06 |= MS;
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codec_send(r06);
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#endif
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return RT_EOK;
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}
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static rt_err_t codec_close(rt_device_t dev)
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{
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/* interrupt mode */
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if (dev->flag & RT_DEVICE_FLAG_INT_TX)
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{
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/* Disable the I2S2 */
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I2S_Cmd(SPI2, DISABLE);
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}
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#if CODEC_MASTER_MODE
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else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
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{
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DMA_Cmd(DMA1_Channel5, DISABLE);
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I2S_Cmd(SPI2, DISABLE);
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r06 &= ~MS;
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codec_send(r06);
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}
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#endif
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/* remove all data node */
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return RT_EOK;
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}
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static rt_err_t codec_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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/* rate control */
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return RT_EOK;
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}
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static rt_size_t codec_write(rt_device_t dev, rt_off_t pos,
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const void* buffer, rt_size_t size)
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{
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struct codec_device* device;
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struct codec_data_node* node;
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rt_uint32_t level;
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rt_uint16_t next_index;
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device = (struct codec_device*) dev;
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RT_ASSERT(device != RT_NULL);
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next_index = device->put_index + 1;
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if (next_index >= DATA_NODE_MAX)
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next_index = 0;
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/* check data_list full */
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if (next_index == device->read_index)
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{
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rt_set_errno(-RT_EFULL);
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return 0;
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}
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level = rt_hw_interrupt_disable();
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node = &device->data_list[device->put_index];
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device->put_index = next_index;
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// rt_kprintf("+\n");
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/* set node attribute */
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node->data_ptr = (rt_uint16_t*) buffer;
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node->data_size = size >> 1; /* size is byte unit, convert to half word unit */
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next_index = device->read_index + 1;
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if (next_index >= DATA_NODE_MAX)
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next_index = 0;
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/* check data list whether is empty */
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if (next_index == device->put_index)
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{
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if (dev->flag & RT_DEVICE_FLAG_INT_TX)
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{
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device->offset = 0;
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/* enable I2S interrupt */
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|
SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, ENABLE);
|
|
}
|
|
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
|
|
{
|
|
DMA_Configuration((rt_uint32_t) node->data_ptr, node->data_size);
|
|
}
|
|
}
|
|
rt_hw_interrupt_enable(level);
|
|
|
|
return size;
|
|
}
|
|
|
|
rt_err_t codec_hw_init(void)
|
|
{
|
|
rt_device_t dev;
|
|
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
|
|
|
|
NVIC_Configuration();
|
|
GPIO_Configuration();
|
|
I2S_Configuration();
|
|
|
|
dev = (rt_device_t) &codec;
|
|
dev->type = RT_Device_Class_Sound;
|
|
dev->rx_indicate = RT_NULL;
|
|
dev->tx_complete = RT_NULL;
|
|
dev->init = codec_init;
|
|
dev->open = codec_open;
|
|
dev->close = codec_close;
|
|
dev->read = RT_NULL;
|
|
dev->write = codec_write;
|
|
dev->control = codec_control;
|
|
dev->private = RT_NULL;
|
|
|
|
/* set read_index and put index to 0 */
|
|
codec.read_index = 0;
|
|
codec.put_index = 0;
|
|
|
|
/* unselect */
|
|
codec_set_csb();
|
|
|
|
/* register the device */
|
|
return rt_device_register(&codec.parent, "snd", RT_DEVICE_FLAG_WRONLY | RT_DEVICE_FLAG_DMA_TX);
|
|
}
|
|
|
|
void codec_isr()
|
|
{
|
|
struct codec_data_node* node;
|
|
node = &codec.data_list[codec.read_index]; /* get current data node */
|
|
|
|
if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_TXE) == SET)
|
|
{
|
|
SPI_I2S_SendData(SPI2, node->data_ptr[codec.offset++]);
|
|
}
|
|
|
|
if (codec.offset == node->data_size)
|
|
{
|
|
/* move to next node */
|
|
rt_uint16_t next_index;
|
|
|
|
next_index = codec.read_index + 1;
|
|
if (next_index >= DATA_NODE_MAX)
|
|
next_index = 0;
|
|
|
|
/* notify transmitted complete. */
|
|
if (codec.parent.tx_complete != RT_NULL)
|
|
{
|
|
codec.parent.tx_complete(&codec.parent,
|
|
codec.data_list[codec.read_index].data_ptr);
|
|
rt_kprintf("-\n");
|
|
}
|
|
|
|
codec.offset = 0;
|
|
codec.read_index = next_index;
|
|
if (next_index == codec.put_index)
|
|
{
|
|
/* no data on the list, disable I2S interrupt */
|
|
SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
|
|
|
|
rt_kprintf("*\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
void codec_dma_isr()
|
|
{
|
|
/* switch to next buffer */
|
|
rt_uint16_t next_index;
|
|
void* data_ptr;
|
|
|
|
next_index = codec.read_index + 1;
|
|
if (next_index >= DATA_NODE_MAX)
|
|
next_index = 0;
|
|
|
|
/* save current data pointer */
|
|
data_ptr = codec.data_list[codec.read_index].data_ptr;
|
|
|
|
codec.read_index = next_index;
|
|
if (next_index != codec.put_index)
|
|
{
|
|
/* enable next dma request */
|
|
DMA_Configuration((rt_uint32_t) codec.data_list[codec.read_index].data_ptr, codec.data_list[codec.read_index].data_size);
|
|
}
|
|
else
|
|
{
|
|
#if CODEC_MASTER_MODE
|
|
DMA_ZeroFill_I2S();
|
|
#endif
|
|
|
|
rt_kprintf("*\n");
|
|
}
|
|
|
|
/* notify transmitted complete. */
|
|
if (codec.parent.tx_complete != RT_NULL)
|
|
{
|
|
codec.parent.tx_complete(&codec.parent, data_ptr);
|
|
// rt_kprintf("-\n");
|
|
}
|
|
}
|