577 lines
22 KiB
C
577 lines
22 KiB
C
//*****************************************************************************
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//
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// am_hal_cachectrl.c
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//! @file
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//!
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//! @brief Functions for interfacing with the CACHE controller.
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//!
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//! @addtogroup clkgen2 Clock Generator (CACHE)
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//! @ingroup apollo2hal
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//! @{
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#include <stdint.h>
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#include <stdbool.h>
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#include "am_mcu_apollo.h"
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//*****************************************************************************
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//
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// Default settings for the cache.
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//
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//*****************************************************************************
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const am_hal_cachectrl_config_t am_hal_cachectrl_defaults =
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{
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1, // ui32EnableCache
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0, // ui32LRU
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0, // ui32EnableNCregions
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AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512, // ui32Config
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0, // ui32SerialCacheMode
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3, // ui32FlashCachingEnables
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1, // ui32EnableCacheClockGating
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0, // ui32EnableLightSleep
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1, // ui32Dly
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1, // ui32SMDly
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1, // ui32EnableDataClockGating
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0, // ui32EnableCacheMonitoring
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};
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//*****************************************************************************
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//
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//! @brief Enable the cache using the supplied settings
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//!
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//! @param psConfig - pointer to a config structure containing cache settings.
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//!
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//! This function takes in a structure of cache settings, and uses them to
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//! enable the cache. This function will take care of the necessary register
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//! writes both in this module and in the power control module, so a separate
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//! powerctrl call is not necessary.
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//!
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//! For most applications, the default cache settings will be the most
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//! efficient choice. To use the default cache settings with this function, use
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//! the address of the global am_hal_cachectrl_defaults structure as the
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//! psConfig argument.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig)
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{
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uint32_t ui32ConfigValue;
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uint32_t ui32Timeout;
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//
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// Pull the configuration data from the structure, and prepare to write the
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// cache configuration register.
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//
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// NOTE: ICACHE and DCACHE settings were left out from this step. This is a
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// workaround for a timing issue with early versions of Apollo2 that caused
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// the cache to incorrectly mark itself valid during the startup sequence.
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// The workaround calls for us to start the cache, manually invalidate it,
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// and then enable ICACHE and DCACHE operation.
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//
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ui32ConfigValue = (AM_REG_CACHECTRL_CACHECFG_ENABLE( 1 ) |
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AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU ) |
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( (psConfig->ui32EnableNCregions & 0x1) >> 0 ) |
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( (psConfig->ui32EnableNCregions & 0x2) >> 1 ) |
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psConfig->ui32Config |
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AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode) |
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AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( psConfig->ui32EnableCacheClockGating ) |
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AM_REG_CACHECTRL_CACHECFG_CACHE_LS(psConfig->ui32EnableLightSleep ) |
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AM_REG_CACHECTRL_CACHECFG_DLY( psConfig->ui32Dly ) |
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AM_REG_CACHECTRL_CACHECFG_SMDLY( psConfig->ui32SMDly ) |
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AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(psConfig->ui32EnableDataClockGating) |
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AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(psConfig->ui32EnableCacheMonitoring) );
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//
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// Make sure the cache is enabled in the power control block.
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//
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am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE);
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//
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// Set the initial cache settings.
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//
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AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue;
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//
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// Wait for the cache ready signal.
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//
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for (ui32Timeout = 0; ui32Timeout < 50; ui32Timeout++)
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{
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if (AM_BFM(CACHECTRL, CACHECTRL, CACHE_READY))
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{
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break;
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}
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}
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//
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// Manually invalidate the cache (workaround for the issue described above.)
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//
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AM_BFW(CACHECTRL, CACHECTRL, INVALIDATE, 1);
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//
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// Wait for the cache ready signal again.
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//
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for (ui32Timeout = 0; ui32Timeout < 50; ui32Timeout++)
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{
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if (AM_BFM(CACHECTRL, CACHECTRL, CACHE_READY))
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{
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break;
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}
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}
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//
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// Now that the cache is running, and correctly marked invalid, we can OR in
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// the ICACHE and DCACHE settings.
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//
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ui32ConfigValue |= (AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( (psConfig->ui32FlashCachingEnables & 0x1) >> 0 ) |
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AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( (psConfig->ui32FlashCachingEnables & 0x2) >> 1 ) );
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//
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// Write the final configuration settings to the CACHECTRL register.
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//
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AM_REG(CACHECTRL, CACHECFG) = ui32ConfigValue;
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}
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//*****************************************************************************
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//
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//! @brief Disable the cache.
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//!
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//! Call this function to completely shut down cache features.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_cachectrl_disable(void)
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{
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uint32_t ui32CacheCfg;
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//
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// Save the cache settings.
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//
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ui32CacheCfg = AM_REG(CACHECTRL, CACHECFG);
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//
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// Remove the ICACHE and DCACHE settings.
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//
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ui32CacheCfg &= (AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(0) |
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AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(0));
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//
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// Write the resulting value back to the register.
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//
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AM_REG(CACHECTRL, CACHECFG) = ui32CacheCfg;
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//
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// Read the CACHECTRL register a few times
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//
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AM_REG(CACHECTRL, CACHECTRL);
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AM_REG(CACHECTRL, CACHECTRL);
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AM_REG(CACHECTRL, CACHECTRL);
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//
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// Disable the cache completely.
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//
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AM_BFW(CACHECTRL, CACHECFG, ENABLE, 0);
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//
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// Power the cache down in the powerctrl block.
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//
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am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE_DIS);
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}
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//*****************************************************************************
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//
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//! @brief Set a default cache configuration.
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//!
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//! This function is used to set a default cache configuration.
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//
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//*****************************************************************************
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void
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am_hal_cachectrl_config_default(void)
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{
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//
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// Set PWRCTRL
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//
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am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_CACHE);
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//
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// Write a default configuration to the CACHECFG register.
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//
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AM_REG(CACHECTRL, CACHECFG) = \
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AM_REG_CACHECTRL_CACHECFG_ENABLE( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_LRU( 0 ) | \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0( 0 ) | \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1( 0 ) | \
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AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E | \
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AM_REG_CACHECTRL_CACHECFG_SERIAL( 0 ) | \
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AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_CACHE_LS( 0 ) | \
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AM_REG_CACHECTRL_CACHECFG_DLY( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_SMDLY( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE( 1 ) | \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR( 0 );
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//
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// Write a default configuration to the FLASHCFG register.
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//
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AM_REG(CACHECTRL, FLASHCFG) = AM_REG_CACHECTRL_FLASHCFG_RD_WAIT(1);
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//
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// Write a default configuration to the CACHECTRL register.
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//
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AM_REG(CACHECTRL, CACHECTRL) = \
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AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE(1) | \
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AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE(0) | \
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AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE(1) | \
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AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE(0) | \
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AM_REG_CACHECTRL_CACHECTRL_RESET_STAT(0) | \
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AM_REG_CACHECTRL_CACHECTRL_INVALIDATE(0);
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//
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// Write a default configuration to the NCR0START and NCR0END registers.
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//
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AM_REG(CACHECTRL, NCR0START) = \
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AM_REG_CACHECTRL_NCR0START_ADDR(0);
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AM_REG(CACHECTRL, NCR0END) = \
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AM_REG_CACHECTRL_NCR0END_ADDR(0);
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//
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// Write a default configuration to the NCR1START and NCR1END registers.
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//
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AM_REG(CACHECTRL, NCR1START) = \
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AM_REG_CACHECTRL_NCR1START_ADDR(0);
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AM_REG(CACHECTRL, NCR1END) = \
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AM_REG_CACHECTRL_NCR1END_ADDR(0);
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//
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// Write a default configuration to the DMONn and IMONn registers.
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//
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AM_REG(CACHECTRL, DMON0) = \
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AM_REG_CACHECTRL_DMON0_DACCESS_COUNT(0);
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AM_REG(CACHECTRL, DMON1) = \
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AM_REG_CACHECTRL_DMON1_DLOOKUP_COUNT(0);
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AM_REG(CACHECTRL, DMON2) = \
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AM_REG_CACHECTRL_DMON2_DHIT_COUNT(0);
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AM_REG(CACHECTRL, DMON3) = \
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AM_REG_CACHECTRL_DMON3_DLINE_COUNT(0);
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AM_REG(CACHECTRL, IMON0) = \
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AM_REG_CACHECTRL_IMON0_IACCESS_COUNT(0);
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AM_REG(CACHECTRL, IMON1) = \
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AM_REG_CACHECTRL_IMON1_ILOOKUP_COUNT(0);
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AM_REG(CACHECTRL, IMON2) = \
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AM_REG_CACHECTRL_IMON2_IHIT_COUNT(0);
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AM_REG(CACHECTRL, IMON3) = \
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AM_REG_CACHECTRL_IMON3_ILINE_COUNT(0);
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}
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//*****************************************************************************
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//
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//! @brief Enable the flash cache controller via a configuration structure.
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//!
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//! @param psConfig - Pointer to a data structure containing all of the data
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// necessary to configure the CACHECFG register.
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//!
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//! This function is used to configure all fields of the CACHECFG.
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//
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//*****************************************************************************
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void
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am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig)
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{
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uint32_t u32ConfigValue;
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//
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// Arrange all of the members of the data structure into a single u32 that
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// can be written to the register.
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//
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u32ConfigValue =
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AM_REG_CACHECTRL_CACHECFG_ENABLE( psConfig->ui32EnableCache ) |
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AM_REG_CACHECTRL_CACHECFG_LRU( psConfig->ui32LRU ) |
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0(
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(psConfig->ui32EnableNCregions & 0x1) >> 0 ) |
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1(
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(psConfig->ui32EnableNCregions & 0x2) >> 1 ) |
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psConfig->ui32Config |
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AM_REG_CACHECTRL_CACHECFG_SERIAL(psConfig->ui32SerialCacheMode) |
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AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE(
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(psConfig->ui32FlashCachingEnables & 0x1) >> 0 ) |
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AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE(
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(psConfig->ui32FlashCachingEnables & 0x2) >> 1 ) |
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AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE(
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psConfig->ui32EnableCacheClockGating ) |
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AM_REG_CACHECTRL_CACHECFG_CACHE_LS(
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psConfig->ui32EnableLightSleep ) |
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AM_REG_CACHECTRL_CACHECFG_DLY( psConfig->ui32Dly ) |
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AM_REG_CACHECTRL_CACHECFG_SMDLY( psConfig->ui32SMDly ) |
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AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE(
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psConfig->ui32EnableDataClockGating ) |
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AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR(
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psConfig->ui32EnableCacheMonitoring );
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//
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// Write the configuration value to the CACHECFG register.
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//
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AM_REG(CACHECTRL, CACHECFG) = u32ConfigValue;
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}
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//*****************************************************************************
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//
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//! @brief Configure the various flash cache controller enables.
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//!
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//! @param u32EnableMask - Mask of features to be enabled.
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//! @param u32DisableMask - Mask of features to be disabled.
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//!
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//! This function is used to enable or disable the various flash cache
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//! controller configuration enables which consist of the following:
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//! AM_HAL_CACHECTRL_CACHECFG_ENABLE Flash cache controller
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//! AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE LRU (disabled = LRR)
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//! AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE Non-cacheable region 0
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//! AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE Non-cacheable region 1
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//! AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE Serial cache mode
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//! AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE Instruction caching
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//! AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE Data caching.
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//! AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE Cache clock gating
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//! AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE Light sleep cache RAMs
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//! AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE Data clock gating
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//! AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE Cache Monitoring Stats
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//!
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//! Note that if both an enable and disable are provided in their respective
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//! masks, the enable will take precendence.
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//!
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//! @return The previous status of the flash cache controller enables.
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//
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//*****************************************************************************
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#define CACHECTRL_VALID_ENABLES ( \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_M | \
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AM_REG_CACHECTRL_CACHECFG_LRU_M | \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M | \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M | \
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AM_REG_CACHECTRL_CACHECFG_SERIAL_M | \
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AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M | \
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AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M | \
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AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M | \
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AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M | \
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AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M | \
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AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M )
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uint32_t
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am_hal_cachectrl_cache_enables(uint32_t u32EnableMask, uint32_t u32DisableMask)
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{
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uint32_t ui32RetVal = AM_BFR(CACHECTRL, CACHECFG, ENABLE) &
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CACHECTRL_VALID_ENABLES;
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//
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// Make sure the enable masks include only valid bits.
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//
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u32EnableMask &= CACHECTRL_VALID_ENABLES;
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u32DisableMask &= CACHECTRL_VALID_ENABLES;
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//
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// First, do the disables.
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//
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AM_REG(CACHECTRL, CACHECFG) &= ~u32DisableMask;
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//
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// Now set the enables.
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//
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AM_REG(CACHECTRL, CACHECFG) |= u32EnableMask;
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return ui32RetVal;
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}
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//*****************************************************************************
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//
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//! @brief Select the cache configuration type.
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//!
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//! This functions only sets the CACHECFG CONFIG field.
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//!
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//! @param ui32CacheConfig - The cache configuration value.
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//!
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//! This function can be used to select the type of cache.frequency of the main
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//! system clock. The ui32CacheConfig parameter should be set to one of the
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//! following values:
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//!
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//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 : Direct mapped,
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//! 128-bit linesize, 256 entries (2 SRAMs active).
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//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 : Two-way set associative,
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//! 128-bit linesize, 256 entries (4 SRAMs active).
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//! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 : Two-way set associative,
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//! 128-bit linesize, 512 entries (8 SRAMs active).
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig)
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{
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//
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// Clear the bitfield
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//
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AM_REG(CACHECTRL, CACHECFG) &= ~AM_REG_CACHECTRL_CACHECFG_CONFIG_M;
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//
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// Write the new value to the bitfield.
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//
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AM_REG(CACHECTRL, CACHECFG) |= ui32CacheConfig &
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AM_REG_CACHECTRL_CACHECFG_CONFIG_M;
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}
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//*****************************************************************************
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//
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//! @brief Invalidate the flash cache.
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//!
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//! This function is used to invalidate the flash cache.
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//!
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//! @return None.
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//
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//*****************************************************************************
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void
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am_hal_cachectrl_invalidate_flash_cache(void)
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{
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//
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// Write the bit to invalidate the flash cache.
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// Note - this bit is not sticky, no need to write it back to 0.
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//
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AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_INVALIDATE_GO;
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}
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|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Reset cache statistics.
|
|
//!
|
|
//! This function is used to reset cache statistics.
|
|
//!
|
|
//! @return None.
|
|
//
|
|
//*****************************************************************************
|
|
void
|
|
am_hal_cachectrl_reset_statistics(void)
|
|
{
|
|
//
|
|
// Write the bit to reset flash statistics.
|
|
// Note - this bit is not sticky, no need to write it back to 0.
|
|
//
|
|
AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_RESET_STAT_CLEAR;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Get flash cache sleep mode status.
|
|
//!
|
|
//! This function returns flash cache sleep mode statuses.
|
|
//!
|
|
//! @return
|
|
//! bit0 indicates that flash0 flash sleep mode is enabled.
|
|
//! bit1 indicates that flash1 flash sleep mode is enabled.
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
am_hal_cachectrl_sleep_mode_status(void)
|
|
{
|
|
uint32_t ui32Status, ui32Ret;
|
|
|
|
//
|
|
// Get the current sleep mode status bits.
|
|
//
|
|
ui32Status = AM_REG(CACHECTRL, CACHECTRL);
|
|
ui32Ret = (ui32Status & \
|
|
AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_M) >> \
|
|
(AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_STATUS_S - 0);
|
|
ui32Ret |= (ui32Status & \
|
|
AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_M) >> \
|
|
(AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_STATUS_S - 1);
|
|
|
|
return ui32Ret;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
//! @brief Enable or disable flash cache sleep mode.
|
|
//!
|
|
//! This function enables or disables flash cache sleep mode.
|
|
//! @param ui32EnableMask - bit0 for flash0, bit1 for flash1.
|
|
//! @param ui32DisableMask - bit0 for flash0, bit1 for flash1.
|
|
//!
|
|
//! Note that if both an enable and disable are provided in their respective
|
|
//! masks, the enable will take precedence.
|
|
//!
|
|
//! @return Previous status.
|
|
//! bit0 indicates that flash0 flash sleep mode was previously enabled.
|
|
//! bit1 indicates that flash1 flash sleep mode was previously enabled.
|
|
//
|
|
//*****************************************************************************
|
|
uint32_t
|
|
am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask,
|
|
uint32_t ui32DisableMask)
|
|
{
|
|
uint32_t ui32Ret = am_hal_cachectrl_sleep_mode_status();
|
|
|
|
if ( ui32DisableMask & 0x1 )
|
|
{
|
|
AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_DISABLE_M;
|
|
}
|
|
|
|
if ( ui32DisableMask & 0x2 )
|
|
{
|
|
AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_DISABLE_M;
|
|
}
|
|
|
|
if ( ui32EnableMask & 0x1 )
|
|
{
|
|
AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH0_SLM_ENABLE_M;
|
|
}
|
|
|
|
if ( ui32EnableMask & 0x2 )
|
|
{
|
|
AM_REG(CACHECTRL, CACHECTRL) |= AM_REG_CACHECTRL_CACHECTRL_FLASH1_SLM_ENABLE_M;
|
|
}
|
|
|
|
return ui32Ret;
|
|
}
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// End Doxygen group.
|
|
//! @}
|
|
//
|
|
//*****************************************************************************
|