65 lines
2.4 KiB
C
65 lines
2.4 KiB
C
/*
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* File : rt_low_level_init.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-04-14 ArdaFu first version
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*/
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/* write register a=address, v=value */
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#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v))
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/* Processor Reset */
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#define AT91_RSTC_PROCRST (1 << 0)
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#define AT91_RSTC_PERRST (1 << 2)
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#define AT91_RSTC_KEY (0xa5 << 24)
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#define AT91_MATRIX_BASE (0XFFFFEE00)
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/* Master Remap Control Register */
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#define AT91_MATRIX_MRCR (AT91_MATRIX_BASE + 0x100)
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/* Remap Command for AHB Master 0 (ARM926EJ-S InSTRuction Master) */
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#define AT91_MATRIX_RCB0 (1 << 0)
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
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#define AT91_MATRIX_RCB1 (1 << 1)
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#define AT91_AIC_BASE (0XFFFFF000)
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/* Interrupt DisaBLe Command Register */
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#define AT91_AIC_IDCR (AT91_AIC_BASE + 0x124)
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/* Interrupt Clear Command Register */
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#define AT91_AIC_ICCR (AT91_AIC_BASE + 0x128)
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#define AT91_WDT_BASE (0XFFFFFD40)
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#define AT91_WDT_CR (AT91_WDT_BASE + 0x00)
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#define AT91_WDT_CR_KEY (0xA5000000)
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#define AT91_WDT_CR_WDRSTT (0x00000001)
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#define AT91_WDT_MR (AT91_WDT_BASE + 0x04)
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#define AT91_WDT_MR_WDDIS (0x00008000)
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void rt_low_level_init(void)
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{
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// Mask all IRQs by clearing all bits in the INTMRS
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write_reg(AT91_AIC_IDCR, 0xFFFFFFFF);
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write_reg(AT91_AIC_ICCR, 0xFFFFFFFF);
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// Remap internal ram to 0x00000000 Address
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write_reg(AT91_MATRIX_MRCR, AT91_MATRIX_RCB0 | AT91_MATRIX_RCB1);
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// Disable the watchdog
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write_reg(AT91_WDT_CR, AT91_WDT_CR_KEY|AT91_WDT_CR_WDRSTT);
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write_reg(AT91_WDT_MR, AT91_WDT_MR_WDDIS);
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}
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