283 lines
6.5 KiB
C
283 lines
6.5 KiB
C
#include <rthw.h>
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#include <rtthread.h>
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#include <soc3210.h>
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/**
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* @addtogroup Loongson SoC3210
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*/
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/*@{*/
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#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
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/* UART interrupt enable register value */
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#define UARTIER_IME (1 << 3)
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#define UARTIER_ILE (1 << 2)
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#define UARTIER_ITXE (1 << 1)
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#define UARTIER_IRXE (1 << 0)
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/* UART line control register value */
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#define UARTLCR_DLAB (1 << 7)
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#define UARTLCR_BCB (1 << 6)
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#define UARTLCR_SPB (1 << 5)
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#define UARTLCR_EPS (1 << 4)
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#define UARTLCR_PE (1 << 3)
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#define UARTLCR_SB (1 << 2)
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/* UART line status register value */
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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struct rt_uart_soc3210
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{
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struct rt_device parent;
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rt_uint32_t hw_base;
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rt_uint32_t irq;
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/* buffer for reception */
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rt_uint8_t read_index, save_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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}uart_device;
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static void rt_uart_irqhandler(int irqno)
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{
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rt_ubase_t level;
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rt_uint8_t isr;
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struct rt_uart_soc3210* uart = &uart_device;
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/* read interrupt status and clear it */
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isr = UART_IIR(uart->hw_base);
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isr = (isr >> 1) & 0x3;
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if (isr & 0x02) /* receive data available */
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{
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/* Receive Data Available */
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while (UART_LSR(uart->hw_base) & UARTLSR_DR)
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{
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uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
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level = rt_hw_interrupt_disable();
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uart->save_index ++;
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if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
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uart->save_index = 0;
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rt_hw_interrupt_enable(level);
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}
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/* invoke callback */
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if(uart->parent.rx_indicate != RT_NULL)
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{
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rt_size_t length;
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if (uart->read_index > uart->save_index)
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length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
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else
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length = uart->save_index - uart->read_index;
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uart->parent.rx_indicate(&uart->parent, length);
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}
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}
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return;
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}
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static rt_err_t rt_uart_init (rt_device_t dev)
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{
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rt_uint32_t baud_div;
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struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
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RT_ASSERT(uart != RT_NULL);
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#if 0
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/* init UART Hardware */
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UART_IER(uart->hw_base) = 0; /* clear interrupt */
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UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
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/* enable UART clock */
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/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
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UART_LCR(uart->hw_base) = 0x3;
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/* set baudrate */
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baud_div = DEV_CLK / 16 / UART_BAUDRATE;
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UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
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UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
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UART_LSB(uart->hw_base) = baud_div & 0xff;
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UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
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/* Enable UART unit, enable and clear FIFO */
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UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
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#endif
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return RT_EOK;
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}
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static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
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{
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struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
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RT_ASSERT(uart != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Enable the UART Interrupt */
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UART_IER(uart->hw_base) |= UARTIER_IRXE;
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/* install interrupt */
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rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL);
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rt_hw_interrupt_umask(uart->irq);
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}
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return RT_EOK;
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}
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static rt_err_t rt_uart_close(rt_device_t dev)
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{
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struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
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RT_ASSERT(uart != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Disable the UART Interrupt */
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UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
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}
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return RT_EOK;
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}
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static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_uint8_t* ptr;
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struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
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RT_ASSERT(uart != RT_NULL);
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/* point to buffer */
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ptr = (rt_uint8_t*) buffer;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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while (size)
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{
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/* interrupt receive */
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rt_base_t level;
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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if (uart->read_index != uart->save_index)
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{
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*ptr = uart->rx_buffer[uart->read_index];
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uart->read_index ++;
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if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
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uart->read_index = 0;
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}
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else
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{
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/* no data in rx buffer */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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break;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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ptr ++;
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size --;
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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return 0;
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}
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static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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char *ptr;
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struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
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RT_ASSERT(uart != RT_NULL);
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ptr = (char*)buffer;
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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/* FIFO status, contain valid data */
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while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
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/* write data */
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UART_DAT(uart->hw_base) = '\r';
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}
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/* FIFO status, contain valid data */
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while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
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/* write data */
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UART_DAT(uart->hw_base) = *ptr;
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ptr ++;
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size --;
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}
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}
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else
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{
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while ( size != 0 )
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{
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/* FIFO status, contain valid data */
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while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
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/* write data */
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UART_DAT(uart->hw_base) = *ptr;
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ptr++;
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size--;
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}
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}
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return (rt_size_t) ptr - (rt_size_t) buffer;
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}
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void rt_hw_uart_init(void)
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{
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struct rt_uart_soc3210* uart;
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/* get uart device */
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uart = &uart_device;
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/* device initialization */
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uart->parent.type = RT_Device_Class_Char;
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rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
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uart->read_index = uart->save_index = 0;
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#if defined(RT_USING_UART1)
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uart->hw_base = UART0_BASE;
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uart->irq = IRQ_UART0;
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#elif defined(RT_USING_UART2)
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uart->hw_base = UART1_BASE;
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uart->irq = IRQ_UART1;
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#endif
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/* device interface */
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uart->parent.init = rt_uart_init;
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uart->parent.open = rt_uart_open;
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uart->parent.close = rt_uart_close;
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uart->parent.read = rt_uart_read;
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uart->parent.write = rt_uart_write;
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uart->parent.control = RT_NULL;
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uart->parent.user_data = RT_NULL;
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rt_device_register(&uart->parent,
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"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
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}
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#endif /* end of UART */
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/*@}*/
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