276 lines
8.8 KiB
C
276 lines
8.8 KiB
C
/*****************************************************************************
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*
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* Copyright Andes Technology Corporation 2007-2008
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* All Rights Reserved.
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*
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* Revision History:
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*
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* Aug.21.2007 Created.
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****************************************************************************/
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/*****************************************************************************
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*
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* FILE NAME VERSION
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*
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* dmad.h
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*
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* DESCRIPTION
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*
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* DMA controller driver internal supplement library.
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*
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* DATA STRUCTURES
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*
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* None
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*
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* DEPENDENCIES
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*
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* ag101regs.h
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* ag101defs.h
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*
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****************************************************************************/
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#ifndef __DMAD_H__
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#define __DMAD_H__
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#include <hal.h>
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/*****************************************************************************
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* Configuration section
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****************************************************************************/
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/* Code size control */
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#define DMAD_SMALL_FOOTPRINT 0 /* non-zero to disable extra features for small footprint */
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/* Debug trace enable switch */
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#define DMAD_DEBUG_TRACE 0 /* non-zero to enable debug trace message */
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/* DMAD globals section */
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enum DMAD_DMAC_CORE { DMAD_DMAC_AHB_CORE, DMAD_DMAC_APB_CORE };
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/*
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* AHB Channel Request
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*
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* Notes for developers:
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* These should be channel-only properties. Controller-specific properties
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* should be separated as other driver structure or driver buildin-hardcode.
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* If controller properties are embeded in this union, request for a channel
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* may unexpectedly override the controller setting of the request of other
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* channels.
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*/
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typedef struct DMAD_AHBCH_REQUEST_STRUCT{
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/* controller property (removed! should not exist in this struct) */
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// uint8_t big_endian; /* (in) currently only M0 is designed, and transfer endian is default to little */
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/* channel property */
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uint32_t sync; /* (in) non-zero if src and dst have different clock domain */
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uint32_t priority; /* (in) DMAC_CSR_CHPRI_0 (lowest) ~ DMAC_CSR_CHPRI_3 (highest) */
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uint32_t hw_handshake; /* (in) non-zero to enable hardware handshake mode */
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/* (required when need multiple bursts or in chain mode?) */
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uint32_t burst_size; /* (in) DMAC_CSR_SIZE_1 ~ DMAC_CSR_SIZE_256 */
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/* source property */
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uint32_t src_width; /* (in) DMAC_CSR_WIDTH_8, DMAC_CSR_WIDTH_16, or DMAC_CSR_WIDTH_32 */
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uint32_t src_addr_ctrl; /* (in) DMAC_CSR_AD_INC, DMAC_CSR_AD_DEC, or DMAC_CSR_AD_FIX */
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uint32_t src_reqn; /* (in) DMAC_REQN_xxx (also used to help determine channel number) */
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uint32_t src_index;
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/* destination property */
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uint32_t dst_width; /* (in) DMAC_CSR_WIDTH_8, DMAC_CSR_WIDTH_16, or DMAC_CSR_WIDTH_32 */
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uint32_t dst_addr_ctrl; /* (in) DMAC_CSR_AD_INC, DMAC_CSR_AD_DEC, or DMAC_CSR_AD_FIX */
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uint32_t dst_reqn; /* (in) DMAC_REQN_xxx (also used to help determine channel number) */
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uint32_t dst_index;
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} DMAD_AHBCH_REQUEST;
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/*
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* APB Channel Request
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*
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* Notes for developers:
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* These should be channel-only properties. Controller-specific properties
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* should be separated as other driver structure or driver buildin-hardcode.
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* If controller properties are embeded in this union, request for a channel
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* may unexpectedly override the controller setting of the request of other
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* channels.
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*/
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typedef struct DMAD_APBCH_REQUEST_STRUCT{
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/* controller property (removed! should not exist in this struct) */
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/* channel property */
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uint32_t burst_mode; /* (in) Burst mode (0: no burst 1-, 1: burst 4- data cycles per dma cycle) */
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uint32_t data_width; /* (in) APBBR_DATAWIDTH_4(word), APBBR_DATAWIDTH_2(half-word), APBBR_DATAWIDTH_1(byte) */
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/* source property */
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uint32_t src_addr_ctrl; /* (in) APBBR_ADDRINC_xxx */
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uint32_t src_reqn; /* (in) APBBR_REQN_xxx (also used to help determine bus selection) */
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uint32_t src_index;
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/* destination property */
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uint32_t dst_addr_ctrl; /* (in) APBBR_ADDRINC_xxx */
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uint32_t dst_reqn; /* (in) APBBR_REQN_xxx (also used to help determine bus selection) */
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uint32_t dst_index;
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} DMAD_APBCH_REQUEST;
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/* Channel Request Descriptor */
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typedef struct DMAD_CHANNEL_REQUEST_DESC_STRUCT{
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uint32_t controller; /* (in) Use DMA controller in AHB or APB - one of the enum value of DMAD_DMAC_CORE */
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uint32_t channel; /* (out) Allocated/granted channel */
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void *drq; /* (out) Handle to DMA request queue (ptr to DMAD_DRQ, internal use) */
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/*
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* Properties for channel-alloc request
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* Notes for developers:
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* These should be channel-only properties. Controller-specific properties
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* should be separated as other driver structure or driver buildin-hardcode.
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* If controller properties are embeded in this union, request for a channel
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* may unexpectedly override the controller setting of the request of other
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* channels.
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*/
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union {
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DMAD_AHBCH_REQUEST ahbch_req; /* (in) parameters for AHB DMAC channel request */
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DMAD_APBCH_REQUEST apbch_req; /* (in) parameters for APB Bridge embeded DMA conteoller channel request */
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};
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} DMAD_CHANNEL_REQUEST_DESC;
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enum DMAD_DRB_STATE{
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DMAD_DRB_STATE_FREE = 0,
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DMAD_DRB_STATE_READY,
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DMAD_DRB_STATE_SUBMITTED,
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DMAD_DRB_STATE_TRANSFERRING,
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DMAD_DRB_STATE_COMPLETED,
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DMAD_DRB_STATE_ERROR,
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DMAD_DRB_STATE_ABORT,
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};
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/* DMA request block */
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typedef struct DMAD_DRB_STRUCT{
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uint32_t prev; /* (internal) Linked list previous node */
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uint32_t next; /* (internal) Linked list next node */
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uint32_t node; /* (internal) Linked list this node */
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uint32_t state; /* (out) DRB's current state in the whole submission cycle. */
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void *src_addr; /* (in) Source address in this request */
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void *dst_addr; /* (in) Destination address in this submission request */
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uint32_t req_size; /* (in) AHB DMA (12 bits): 0 ~ 4095, unit is number of "data width" */
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/* APB DMA (24 bits): 0 ~ 16M-1, unit is number of "data width * burst size" */
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uint32_t transfer_size; /* req_size * data_width*/
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hal_semaphore_t *completion_sem;/* (in) Application supplied semaphore to signal completion of this */
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/* DMA request block. Specify null to by-pass this mechanism. */
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void (*psp)(void*); /* pre-submission programming */
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void (*rcp)(void*); /* completion-of-submission programming */
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void *data;
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uint32_t src_index; /* to indicate it's device or memory */
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uint32_t dst_index; /* to indicate it's device or memory */
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// uint32_t src_reqn; /* to indicate it's device or memory */
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// uint32_t dst_reqn; /* to indicate it's device or memory */
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} DMAD_DRB;
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enum DMAD_CHDIR
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{
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DMAD_DIR_A0_TO_A1 = 0,
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DMAD_DIR_A1_TO_A0 = 1,
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};
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/* Debug Trace Mechanism */
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#if (DMAD_DEBUG_TRACE)
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#define DMAD_TRACE(x) printf x
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#define DMAD_STRACE(x) printf x
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#else /* DMAD_DEBUG_TRACE */
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#define DMAD_TRACE(x)
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#define DMAD_STRACE(x)
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#endif /* DMAD_DEBUG_TRACE */
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/*****************************************************************************
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* DMAD Driver Interface
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*
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* [Structures]
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*
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* [Functions]
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*
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*
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****************************************************************************/
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extern uint32_t _dmad_channel_alloc(DMAD_CHANNEL_REQUEST_DESC *ch_req, uint8_t init);
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extern uint32_t _dmad_channel_free(const DMAD_CHANNEL_REQUEST_DESC *ch_req);
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extern uint32_t _dmad_channel_init(const DMAD_CHANNEL_REQUEST_DESC *ch_req);
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extern uint32_t _dmad_channel_enable(const DMAD_CHANNEL_REQUEST_DESC *ch_req, uint8_t enable);
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extern uint32_t _dmad_alloc_drb(DMAD_CHANNEL_REQUEST_DESC *ch_req, DMAD_DRB **drb);
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extern uint32_t _dmad_free_drb(DMAD_CHANNEL_REQUEST_DESC *ch_req, DMAD_DRB *drb);
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extern uint32_t _dmad_submit_request(DMAD_CHANNEL_REQUEST_DESC *ch_req, DMAD_DRB *drb);
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extern uint32_t _dmad_cancel_request(DMAD_CHANNEL_REQUEST_DESC *ch_req, DMAD_DRB *drb);
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extern uint32_t _dmad_wait(DMAD_CHANNEL_REQUEST_DESC *ch_req);
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extern uint32_t _dmad_get_reqn(uint32_t dma_controller, uint32_t device);
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enum ahp_reqn_index_t {
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AHB_NONE,
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AHB_CFC,
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AHB_SSP,
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AHB_UART1TX,
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AHB_UART1RX,
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AHB_I2SAC97,
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AHB_USB,
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AHB_EXT0,
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AHB_EXT1,
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AHB_SSP1TX,
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AHB_SSP1RX,
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AHB_UART2TX,
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AHB_UART2RX,
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AHB_UART4TX,
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AHB_UART4RX,
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AHB_SDC,
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AHB_SSP2TX,
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AHB_SSP2RX,
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AHB_USB_2_0,
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AHB_USB_1_1_EP1,
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AHB_USB_1_1_EP2,
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AHB_USB_1_1_EP3,
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AHB_USB_1_1_EP4
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};
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enum apb_reqn_index_t {
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APB_NONE,
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APB_CFC,
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APB_SSP,
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APB_BTUART,
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APB_I2SAC97,
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APB_STUART,
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APB_I2S,
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APB_SSP2,
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APB_EXT0,
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APB_EXT1,
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APB_SSP1TX,
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APB_SSP1RX,
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APB_UART2TX,
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APB_UART2RX,
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APB_UART4TX,
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APB_UART4RX,
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APB_SDC,
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APB_SSP2TX,
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APB_SSP2RX,
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APB_USB_2_0,
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APB_USB_1_1_EP1,
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APB_USB_1_1_EP2,
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APB_USB_1_1_EP3,
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APB_USB_1_1_EP4,
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APB_MAX
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};
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#endif /* __DMAD_H__ */
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