301 lines
18 KiB
C
301 lines
18 KiB
C
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
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* File Name : stm32f10x_adc.h
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* Author : MCD Application Team
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* Version : V2.0.3
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* Date : 09/22/2008
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* Description : This file contains all the functions prototypes for the
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* ADC firmware library.
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********************************************************************************
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_ADC_H
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#define __STM32F10x_ADC_H
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_map.h"
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/* Exported types ------------------------------------------------------------*/
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/* ADC Init structure definition */
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typedef struct
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{
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u32 ADC_Mode;
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FunctionalState ADC_ScanConvMode;
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FunctionalState ADC_ContinuousConvMode;
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u32 ADC_ExternalTrigConv;
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u32 ADC_DataAlign;
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u8 ADC_NbrOfChannel;
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}ADC_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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#define IS_ADC_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
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((*(u32*)&(PERIPH)) == ADC2_BASE) || \
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((*(u32*)&(PERIPH)) == ADC3_BASE))
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#define IS_ADC_DMA_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == ADC1_BASE) || \
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((*(u32*)&(PERIPH)) == ADC3_BASE))
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/* ADC dual mode -------------------------------------------------------------*/
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#define ADC_Mode_Independent ((u32)0x00000000)
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#define ADC_Mode_RegInjecSimult ((u32)0x00010000)
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#define ADC_Mode_RegSimult_AlterTrig ((u32)0x00020000)
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#define ADC_Mode_InjecSimult_FastInterl ((u32)0x00030000)
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#define ADC_Mode_InjecSimult_SlowInterl ((u32)0x00040000)
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#define ADC_Mode_InjecSimult ((u32)0x00050000)
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#define ADC_Mode_RegSimult ((u32)0x00060000)
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#define ADC_Mode_FastInterl ((u32)0x00070000)
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#define ADC_Mode_SlowInterl ((u32)0x00080000)
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#define ADC_Mode_AlterTrig ((u32)0x00090000)
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#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
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((MODE) == ADC_Mode_RegInjecSimult) || \
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((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
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((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
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((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
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((MODE) == ADC_Mode_InjecSimult) || \
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((MODE) == ADC_Mode_RegSimult) || \
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((MODE) == ADC_Mode_FastInterl) || \
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((MODE) == ADC_Mode_SlowInterl) || \
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((MODE) == ADC_Mode_AlterTrig))
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/* ADC extrenal trigger sources for regular channels conversion --------------*/
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/* for ADC1 and ADC2 */
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#define ADC_ExternalTrigConv_T1_CC1 ((u32)0x00000000)
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#define ADC_ExternalTrigConv_T1_CC2 ((u32)0x00020000)
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#define ADC_ExternalTrigConv_T2_CC2 ((u32)0x00060000)
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#define ADC_ExternalTrigConv_T3_TRGO ((u32)0x00080000)
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#define ADC_ExternalTrigConv_T4_CC4 ((u32)0x000A0000)
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#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((u32)0x000C0000)
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/* for ADC1, ADC2 and ADC3 */
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#define ADC_ExternalTrigConv_T1_CC3 ((u32)0x00040000)
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#define ADC_ExternalTrigConv_None ((u32)0x000E0000)
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/* for ADC3 */
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#define ADC_ExternalTrigConv_T3_CC1 ((u32)0x00000000)
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#define ADC_ExternalTrigConv_T2_CC3 ((u32)0x00020000)
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#define ADC_ExternalTrigConv_T8_CC1 ((u32)0x00060000)
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#define ADC_ExternalTrigConv_T8_TRGO ((u32)0x00080000)
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#define ADC_ExternalTrigConv_T5_CC1 ((u32)0x000A0000)
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#define ADC_ExternalTrigConv_T5_CC3 ((u32)0x000C0000)
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#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
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((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
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((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
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((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
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((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
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((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
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((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
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((REGTRIG) == ADC_ExternalTrigConv_None) || \
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((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
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((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
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((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
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((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
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((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
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((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
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/* ADC data align ------------------------------------------------------------*/
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#define ADC_DataAlign_Right ((u32)0x00000000)
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#define ADC_DataAlign_Left ((u32)0x00000800)
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#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
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((ALIGN) == ADC_DataAlign_Left))
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/* ADC channels --------------------------------------------------------------*/
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#define ADC_Channel_0 ((u8)0x00)
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#define ADC_Channel_1 ((u8)0x01)
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#define ADC_Channel_2 ((u8)0x02)
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#define ADC_Channel_3 ((u8)0x03)
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#define ADC_Channel_4 ((u8)0x04)
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#define ADC_Channel_5 ((u8)0x05)
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#define ADC_Channel_6 ((u8)0x06)
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#define ADC_Channel_7 ((u8)0x07)
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#define ADC_Channel_8 ((u8)0x08)
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#define ADC_Channel_9 ((u8)0x09)
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#define ADC_Channel_10 ((u8)0x0A)
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#define ADC_Channel_11 ((u8)0x0B)
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#define ADC_Channel_12 ((u8)0x0C)
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#define ADC_Channel_13 ((u8)0x0D)
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#define ADC_Channel_14 ((u8)0x0E)
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#define ADC_Channel_15 ((u8)0x0F)
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#define ADC_Channel_16 ((u8)0x10)
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#define ADC_Channel_17 ((u8)0x11)
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#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
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((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
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((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
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((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
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((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
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((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
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((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
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((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
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((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
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/* ADC sampling times --------------------------------------------------------*/
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#define ADC_SampleTime_1Cycles5 ((u8)0x00)
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#define ADC_SampleTime_7Cycles5 ((u8)0x01)
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#define ADC_SampleTime_13Cycles5 ((u8)0x02)
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#define ADC_SampleTime_28Cycles5 ((u8)0x03)
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#define ADC_SampleTime_41Cycles5 ((u8)0x04)
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#define ADC_SampleTime_55Cycles5 ((u8)0x05)
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#define ADC_SampleTime_71Cycles5 ((u8)0x06)
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#define ADC_SampleTime_239Cycles5 ((u8)0x07)
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#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
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((TIME) == ADC_SampleTime_7Cycles5) || \
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((TIME) == ADC_SampleTime_13Cycles5) || \
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((TIME) == ADC_SampleTime_28Cycles5) || \
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((TIME) == ADC_SampleTime_41Cycles5) || \
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((TIME) == ADC_SampleTime_55Cycles5) || \
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((TIME) == ADC_SampleTime_71Cycles5) || \
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((TIME) == ADC_SampleTime_239Cycles5))
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/* ADC extrenal trigger sources for injected channels conversion -------------*/
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/* For ADC1 and ADC2 */
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#define ADC_ExternalTrigInjecConv_T2_TRGO ((u32)0x00002000)
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#define ADC_ExternalTrigInjecConv_T2_CC1 ((u32)0x00003000)
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#define ADC_ExternalTrigInjecConv_T3_CC4 ((u32)0x00004000)
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#define ADC_ExternalTrigInjecConv_T4_TRGO ((u32)0x00005000)
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#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((u32)0x00006000)
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/* For ADC1, ADC2 and ADC3 */
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#define ADC_ExternalTrigInjecConv_T1_TRGO ((u32)0x00000000)
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#define ADC_ExternalTrigInjecConv_T1_CC4 ((u32)0x00001000)
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#define ADC_ExternalTrigInjecConv_None ((u32)0x00007000)
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/* For ADC3 */
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#define ADC_ExternalTrigInjecConv_T4_CC3 ((u32)0x00002000)
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#define ADC_ExternalTrigInjecConv_T8_CC2 ((u32)0x00003000)
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#define ADC_ExternalTrigInjecConv_T8_CC4 ((u32)0x00004000)
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#define ADC_ExternalTrigInjecConv_T5_TRGO ((u32)0x00005000)
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#define ADC_ExternalTrigInjecConv_T5_CC4 ((u32)0x00006000)
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#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
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((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
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/* ADC injected channel selection --------------------------------------------*/
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#define ADC_InjectedChannel_1 ((u8)0x14)
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#define ADC_InjectedChannel_2 ((u8)0x18)
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#define ADC_InjectedChannel_3 ((u8)0x1C)
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#define ADC_InjectedChannel_4 ((u8)0x20)
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#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
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((CHANNEL) == ADC_InjectedChannel_2) || \
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((CHANNEL) == ADC_InjectedChannel_3) || \
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((CHANNEL) == ADC_InjectedChannel_4))
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/* ADC analog watchdog selection ---------------------------------------------*/
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#define ADC_AnalogWatchdog_SingleRegEnable ((u32)0x00800200)
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#define ADC_AnalogWatchdog_SingleInjecEnable ((u32)0x00400200)
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#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((u32)0x00C00200)
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#define ADC_AnalogWatchdog_AllRegEnable ((u32)0x00800000)
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#define ADC_AnalogWatchdog_AllInjecEnable ((u32)0x00400000)
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#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((u32)0x00C00000)
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#define ADC_AnalogWatchdog_None ((u32)0x00000000)
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#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
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((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
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((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
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((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
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((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
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((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
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((WATCHDOG) == ADC_AnalogWatchdog_None))
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/* ADC interrupts definition -------------------------------------------------*/
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#define ADC_IT_EOC ((u16)0x0220)
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#define ADC_IT_AWD ((u16)0x0140)
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#define ADC_IT_JEOC ((u16)0x0480)
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#define IS_ADC_IT(IT) ((((IT) & (u16)0xF81F) == 0x00) && ((IT) != 0x00))
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#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
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((IT) == ADC_IT_JEOC))
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/* ADC flags definition ------------------------------------------------------*/
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#define ADC_FLAG_AWD ((u8)0x01)
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#define ADC_FLAG_EOC ((u8)0x02)
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#define ADC_FLAG_JEOC ((u8)0x04)
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#define ADC_FLAG_JSTRT ((u8)0x08)
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#define ADC_FLAG_STRT ((u8)0x10)
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#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (u8)0xE0) == 0x00) && ((FLAG) != 0x00))
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#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
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((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
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((FLAG) == ADC_FLAG_STRT))
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/* ADC thresholds ------------------------------------------------------------*/
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#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
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/* ADC injected offset -------------------------------------------------------*/
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#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
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/* ADC injected length -------------------------------------------------------*/
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#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
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/* ADC injected rank ---------------------------------------------------------*/
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#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
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/* ADC regular length --------------------------------------------------------*/
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#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
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/* ADC regular rank ----------------------------------------------------------*/
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#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
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/* ADC regular discontinuous mode number -------------------------------------*/
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#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void ADC_DeInit(ADC_TypeDef* ADCx);
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void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
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void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
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void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState);
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void ADC_ResetCalibration(ADC_TypeDef* ADCx);
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FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
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void ADC_StartCalibration(ADC_TypeDef* ADCx);
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FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
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void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
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void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, u8 Number);
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void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
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void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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u16 ADC_GetConversionValue(ADC_TypeDef* ADCx);
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u32 ADC_GetDualModeConversionValue(void);
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void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, u32 ADC_ExternalTrigInjecConv);
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void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
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FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
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void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime);
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void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length);
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void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel, u16 Offset);
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u16 ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, u8 ADC_InjectedChannel);
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void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, u32 ADC_AnalogWatchdog);
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void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, u16 HighThreshold, u16 LowThreshold);
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void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel);
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void ADC_TempSensorVrefintCmd(FunctionalState NewState);
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FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, u8 ADC_FLAG);
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void ADC_ClearFlag(ADC_TypeDef* ADCx, u8 ADC_FLAG);
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ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, u16 ADC_IT);
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void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, u16 ADC_IT);
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#endif /*__STM32F10x_ADC_H */
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/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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