269 lines
7.7 KiB
C
269 lines
7.7 KiB
C
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief Power Manager clocks configuration helper.
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*
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an Atmel
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* AVR product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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*
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*/
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#include <string.h>
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#include "compiler.h"
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#include "pm.h"
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extern void flashc_set_wait_state(unsigned int wait_state);
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#if (defined AVR32_FLASHC_210_H_INCLUDED)
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extern void flashc_issue_command(unsigned int command, int page_number);
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#endif
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#define PM_MAX_MUL ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)
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int pm_configure_clocks(pm_freq_param_t *param)
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{
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// Supported frequencies:
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// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
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// 12 15 1 192 1 12 12
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// 12 9 3 40 1 20 20 PLL out of spec
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// 12 15 1 192 1 24 12
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// 12 9 1 120 1 30 15
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// 12 9 3 40 0 40 20 PLL out of spec
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// 12 15 1 192 1 48 12
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// 12 15 1 192 1 48 24
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// 12 8 1 108 1 54 27
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// 12 9 1 120 1 60 15
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// 12 9 1 120 1 60 30
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// 12 10 1 132 1 66 16.5
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//
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unsigned long in_cpu_f = param->cpu_f;
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unsigned long in_osc0_f = param->osc0_f;
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unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
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unsigned long pll_freq, rest;
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Bool b_div2_pba, b_div2_cpu;
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// Switch to external Oscillator 0
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pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
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// Start with CPU freq config
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if (in_cpu_f == in_osc0_f)
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{
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param->cpu_f = in_osc0_f;
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param->pba_f = in_osc0_f;
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return PM_FREQ_STATUS_OK;
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}
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else if (in_cpu_f < in_osc0_f)
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{
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// TBD
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}
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rest = in_cpu_f % in_osc0_f;
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for (div = 1; div < 32; div++)
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{
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if ((div * rest) % in_osc0_f == 0)
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break;
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}
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if (div == 32)
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return PM_FREQ_STATUS_FAIL;
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mul = (in_cpu_f * div) / in_osc0_f;
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if (mul > PM_MAX_MUL)
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return PM_FREQ_STATUS_FAIL;
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// export 2power from PLL div to div2_cpu
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while (!(div % 2))
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{
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div /= 2;
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div2_cpu++;
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}
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// Here we know the mul and div parameter of the PLL config.
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// . Check out if the PLL has a valid in_cpu_f.
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// . Try to have for the PLL frequency (VCO output) the highest possible value
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// to reduce jitter.
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while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
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{
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if (2 * mul > PM_MAX_MUL)
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break;
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mul *= 2;
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div2_cpu++;
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}
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if (div2_cpu != 0)
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{
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div2_cpu--;
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div2_en = 1;
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}
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pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
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// Update real CPU Frequency
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param->cpu_f = pll_freq / (1 << div2_cpu);
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mul--;
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pm_pll_setup(&AVR32_PM
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, 0 // pll
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, mul // mul
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, div // div
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, 0 // osc
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, 16 // lockcount
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);
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pm_pll_set_option(&AVR32_PM
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, 0 // pll
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// PLL clock is lower than 160MHz: need to set pllopt.
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, (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq
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, div2_en // pll_div2
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, 0 // pll_wbwdisable
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);
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rest = pll_freq;
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while (rest > AVR32_PM_PBA_MAX_FREQ ||
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rest != param->pba_f)
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{
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div2_pba++;
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rest = pll_freq / (1 << div2_pba);
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if (rest < param->pba_f)
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break;
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}
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// Update real PBA Frequency
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param->pba_f = pll_freq / (1 << div2_pba);
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// Enable PLL0
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pm_pll_enable(&AVR32_PM, 0);
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// Wait for PLL0 locked
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pm_wait_for_pll0_locked(&AVR32_PM);
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if (div2_cpu)
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{
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b_div2_cpu = TRUE;
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div2_cpu--;
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}
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else
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b_div2_cpu = FALSE;
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if (div2_pba)
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{
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b_div2_pba = TRUE;
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div2_pba--;
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}
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else
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b_div2_pba = FALSE;
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pm_cksel(&AVR32_PM
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, b_div2_pba, div2_pba // PBA
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, b_div2_cpu, div2_cpu // PBB
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, b_div2_cpu, div2_cpu // HSB
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);
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if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
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{
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flashc_set_wait_state(1);
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#if (defined AVR32_FLASHC_210_H_INCLUDED)
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if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
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flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
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else
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flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
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#endif
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}
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else
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{
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flashc_set_wait_state(0);
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#if (defined AVR32_FLASHC_210_H_INCLUDED)
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if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
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flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
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else
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flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
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#endif
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}
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pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
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return PM_FREQ_STATUS_OK;
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}
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void pm_configure_usb_clock(void)
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{
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#if UC3A3
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// Setup USB GCLK.
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pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
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0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
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0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
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0, // diven
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0); // div
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// Enable USB GCLK.
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pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
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#else
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// Use 12MHz from OSC0 and generate 96 MHz
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pm_pll_setup(&AVR32_PM, 1, // pll.
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7, // mul.
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1, // div.
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0, // osc.
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16); // lockcount.
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pm_pll_set_option(&AVR32_PM, 1, // pll.
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1, // pll_freq: choose the range 80-180MHz.
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1, // pll_div2.
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0); // pll_wbwdisable.
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// start PLL1 and wait forl lock
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pm_pll_enable(&AVR32_PM, 1);
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// Wait for PLL1 locked.
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pm_wait_for_pll1_locked(&AVR32_PM);
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pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
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1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
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1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
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0, // diven.
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0); // div.
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pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
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#endif
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}
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