669 lines
23 KiB
C
669 lines
23 KiB
C
/****************************************************************************
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* $Id:: LPC122x.h 5637 2010-11-18 00:02:05Z nxp28433 $
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* Project: NXP LPC122x software example
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*
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* Description:
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* CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
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* NXP LPC122x Device Series
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*
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****************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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****************************************************************************/
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#ifndef __LPC122x_H__
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#define __LPC122x_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup LPC122x_Definitions LPC122x Definitions
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This file defines all structures and symbols for LPC122x:
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- Registers and bitfields
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- peripheral base address
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- peripheral ID
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- PIO definitions
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@{
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*/
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/******************************************************************************/
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/* Processor and Core Peripherals */
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/******************************************************************************/
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/** @addtogroup LPC122x_CMSIS LPC122x CMSIS Definitions
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Configuration of the Cortex-M0 Processor and Core Peripherals
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@{
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*/
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M0 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M0 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M0 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M0 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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/****** LPC122x Specific Interrupt Numbers *******************************************************/
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WAKEUP0_IRQn = 0, /*!< The I/O pins can be used as wakeup source. */
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WAKEUP1_IRQn = 1,
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WAKEUP2_IRQn = 2,
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WAKEUP3_IRQn = 3,
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WAKEUP4_IRQn = 4,
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WAKEUP5_IRQn = 5,
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WAKEUP6_IRQn = 6,
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WAKEUP7_IRQn = 7,
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WAKEUP8_IRQn = 8,
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WAKEUP9_IRQn = 9,
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WAKEUP10_IRQn = 10,
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WAKEUP11_IRQn = 11, /*!< 0 through 11 are WAKEUP interrupts */
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I2C_IRQn = 12, /*!< I2C Interrupt */
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TIMER_16_0_IRQn = 13, /*!< 16-bit Timer0 Interrupt */
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TIMER_16_1_IRQn = 14, /*!< 16-bit Timer1 Interrupt */
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TIMER_32_0_IRQn = 15, /*!< 32-bit Timer0 Interrupt */
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TIMER_32_1_IRQn = 16, /*!< 32-bit Timer1 Interrupt */
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SSP_IRQn = 17, /*!< SSP Interrupt */
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UART0_IRQn = 18, /*!< UART0 Interrupt */
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UART1_IRQn = 19, /*!< UART1 Interrupt */
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CMP_IRQn = 20, /*!< Comparator Interrupt */
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ADC_IRQn = 21, /*!< A/D Converter Interrupt */
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WDT_IRQn = 22, /*!< Watchdog timer Interrupt */
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BOD_IRQn = 23, /*!< Brown Out Detect(BOD) Interrupt */
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FLASH_IRQn = 24, /*!< Flash Interrupt */
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EINT0_IRQn = 25, /*!< External Interrupt 0 Interrupt */
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EINT1_IRQn = 26, /*!< External Interrupt 1 Interrupt */
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EINT2_IRQn = 27, /*!< External Interrupt 2 Interrupt */
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PMU_IRQn = 28, /*!< PMU Interrupt */
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DMA_IRQn = 29, /*!< DMA Interrupt */
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RTC_IRQn = 30, /*!< RTC Interrupt */
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EDM_IRQn = 31, /*!< EDT Interrupt */
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/*@}*/ /* end of group LPC122x_CMSIS */
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#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#include "system_LPC122x.h" /* System Header */
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/******************************************************************************/
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/* Device Specific Peripheral Registers structures */
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/******************************************************************************/
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/*------------- System Control (SYSCON) --------------------------------------*/
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/** @addtogroup LPC122x_SYSCON LPC122x System Control Block
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@{
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*/
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typedef struct
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{
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__IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */
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__IO uint32_t PRESETCTRL;
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__IO uint32_t SYSPLLCTRL; /* Sys PLL control */
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__IO uint32_t SYSPLLSTAT;
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uint32_t RESERVED0[4];
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__IO uint32_t SYSOSCCTRL; /* Offset 0x20 */
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__IO uint32_t WDTOSCCTRL;
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__IO uint32_t IRCCTRL;
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uint32_t RESERVED0b;
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__IO uint32_t SYSRESSTAT; /* Offset 0x30 */
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uint32_t RESERVED1[3];
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__IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */
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__IO uint32_t SYSPLLCLKUEN;
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uint32_t RESERVED2[10];
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__IO uint32_t MAINCLKSEL; /* Offset 0x70 */
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__IO uint32_t MAINCLKUEN;
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__IO uint32_t SYSAHBCLKDIV;
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uint32_t RESERVED3[1];
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__IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */
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uint32_t RESERVED4[4];
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__IO uint32_t SSPCLKDIV;
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__IO uint32_t UART0CLKDIV;
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__IO uint32_t UART1CLKDIV;
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__IO uint32_t RTCCLKDIV;
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uint32_t RESERVED5[2];
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__IO uint32_t TRACECLKDIV;
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__IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */
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__IO uint32_t I2CCLKDIV;
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uint32_t RESERVED6[10];
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__IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */
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__IO uint32_t CLKOUTUEN;
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__IO uint32_t CLKOUTDIV;
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uint32_t RESERVED7[5];
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__IO uint32_t PIOPORCAP0; /* Offset 0x100 */
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__IO uint32_t PIOPORCAP1;
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uint32_t RESERVED8[11];
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__IO uint32_t FILTERCLKCFG6;
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__IO uint32_t FILTERCLKCFG5;
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__IO uint32_t FILTERCLKCFG4;
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__IO uint32_t FILTERCLKCFG3; /* Offset 0x140 */
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__IO uint32_t FILTERCLKCFG2;
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__IO uint32_t FILTERCLKCFG1;
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__IO uint32_t FILTERCLKCFG0;
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__IO uint32_t BODCTRL; /* Offset 0x150 */
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uint32_t RESERVED9[1];
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__IO uint32_t SYSTCKCAL;
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uint32_t RESERVED10[5];
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__IO uint32_t INT_IRQ_LATENCY; /* Offset 0x170 */
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__IO uint32_t INTNMI;
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uint32_t RESERVED11[34];
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__IO uint32_t STARTAPRP0; /* Offset 0x200 */
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__IO uint32_t STARTERP0;
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__IO uint32_t STARTRSRP0CLR;
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__IO uint32_t STARTSRP0;
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__IO uint32_t STARTAPRP1;
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__IO uint32_t STARTERP1;
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__IO uint32_t STARTRSRP1CLR;
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__IO uint32_t STARTSRP1;
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uint32_t RESERVED12[4];
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__IO uint32_t PDSLEEPCFG; /* Offset 0x230 */
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__IO uint32_t PDAWAKECFG;
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__IO uint32_t PDRUNCFG;
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uint32_t RESERVED13;
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__IO uint32_t EZHBOOT;
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__IO uint32_t EZHCTRL;
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__IO uint32_t EZHMUXSEL;
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__IO uint32_t EZHARM2EZH;
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__IO uint32_t EZHEZH2ARM;
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__IO uint32_t EZHEZHPC;
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__IO uint32_t EZHEZHSP;
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__IO uint32_t EZHINTERRUPT;
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uint32_t RESERVED14[101];
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__I uint32_t DEVICE_ID;
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} LPC_SYSCON_TypeDef;
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/*------------- Pin Connect Block (IOCON) --------------------------------*/
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/** @addtogroup LPC122x_IOCON LPC122x I/O Configuration Block
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@{
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*/
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typedef struct
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{
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__IO uint32_t PIO2_28; /* 0x00 */
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__IO uint32_t PIO2_29;
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__IO uint32_t PIO0_19;
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__IO uint32_t PIO0_20;
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__IO uint32_t PIO0_21;
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__IO uint32_t PIO0_22;
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__IO uint32_t PIO0_23;
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__IO uint32_t PIO0_24;
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__IO uint32_t SWDIO_PIO0_25; /* 0x20 */
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__IO uint32_t SWCLK_PIO0_26;
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__IO uint32_t PIO0_27;
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__IO uint32_t PIO2_12;
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__IO uint32_t PIO2_13;
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__IO uint32_t PIO2_14;
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__IO uint32_t PIO2_15;
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__IO uint32_t PIO0_28;
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__IO uint32_t PIO0_29; /* 0x40 */
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__IO uint32_t PIO0_0;
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__IO uint32_t PIO0_1;
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__IO uint32_t PIO0_2;
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uint32_t RESERVED0;
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__IO uint32_t PIO0_3;
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__IO uint32_t PIO0_4;
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__IO uint32_t PIO0_5;
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__IO uint32_t PIO0_6; /* 0x60 */
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__IO uint32_t PIO0_7;
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__IO uint32_t PIO0_8;
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__IO uint32_t PIO0_9;
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__IO uint32_t PIO2_0;
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__IO uint32_t PIO2_1;
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__IO uint32_t PIO2_2;
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__IO uint32_t PIO2_3;
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__IO uint32_t PIO2_4; /* 0x80 */
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__IO uint32_t PIO2_5;
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__IO uint32_t PIO2_6;
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__IO uint32_t PIO2_7;
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__IO uint32_t PIO0_10;
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__IO uint32_t PIO0_11;
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__IO uint32_t PIO0_12;
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__IO uint32_t RESET_P0_13;
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__IO uint32_t PIO0_14; /* 0xA0 */
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__IO uint32_t PIO0_15;
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__IO uint32_t PIO0_16;
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__IO uint32_t PIO0_17;
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__IO uint32_t PIO0_18;
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__IO uint32_t PIO0_30;
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__IO uint32_t PIO0_31;
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__IO uint32_t PIO1_0;
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__IO uint32_t PIO1_1; /* 0xC0 */
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__IO uint32_t PIO1_2;
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__IO uint32_t PIO1_3;
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__IO uint32_t PIO1_4;
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__IO uint32_t PIO1_5;
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__IO uint32_t PIO1_6;
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uint32_t RESERVED1[2];
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__IO uint32_t PIO2_8; /* 0xE0 */
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__IO uint32_t PIO2_9;
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__IO uint32_t PIO2_10;
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__IO uint32_t PIO2_11;
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#if 0
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/* LOC registers are no longer needed on LPC122x V1. */
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__IO uint32_t EZH0_LOC;
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__IO uint32_t EZH1_LOC;
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__IO uint32_t CT32B0_0_LOC;
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__IO uint32_t EZH2_LOC;
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__IO uint32_t CT32B0_1_LOC; /* 0x100 */
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__IO uint32_t EZH3_LOC;
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__IO uint32_t CT32B0_2_LOC;
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__IO uint32_t EZH4_LOC;
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__IO uint32_t CT32B0_3_LOC;
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__IO uint32_t EZH5_LOC;
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__IO uint32_t EZH6_LOC;
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__IO uint32_t CT32B1_0_LOC;
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__IO uint32_t EZH7_LOC; /* 0x120 */
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__IO uint32_t CT32B1_1_LOC;
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__IO uint32_t EZH8_LOC;
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__IO uint32_t CT32B1_2_LOC;
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__IO uint32_t EZH9_LOC;
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__IO uint32_t CT32B1_3_LOC;
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__IO uint32_t EZH10_LOC;
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__IO uint32_t EZH11_LOC;
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__IO uint32_t CT16B0_0_LOC; /* 0x140 */
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__IO uint32_t EZH12_LOC;
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__IO uint32_t CT16B0_1_LOC;
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__IO uint32_t EZH13_LOC;
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__IO uint32_t EZH14_LOC;
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__IO uint32_t EZH15_LOC;
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__IO uint32_t CT16B1_0_LOC;
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__IO uint32_t CT16B1_1_LOC;
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#endif
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} LPC_IOCON_TypeDef;
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/*------------- microDMA (DMA) --------------------------*/
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/** @addtogroup LPC122x_DMA LPC122x microDMA
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@{
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*/
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typedef struct
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{
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__I uint32_t STATUS;
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__O uint32_t CFG;
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__IO uint32_t CTRL_BASE_PTR;
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__I uint32_t ALT_CTRL_BASE_PTR;
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__I uint32_t WAITONREQ_STATUS;
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__O uint32_t CHNL_SW_REQUEST;
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__IO uint32_t CHNL_USEBURST_SET;
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__O uint32_t CHNL_USEBURST_CLR;
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__IO uint32_t CHNL_REQ_MASK_SET;
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__O uint32_t CHNL_REQ_MASK_CLR;
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__IO uint32_t CHNL_ENABLE_SET;
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__O uint32_t CHNL_ENABLE_CLR;
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__IO uint32_t CHNL_PRI_ALT_SET;
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__O uint32_t CHNL_PRI_ALT_CLR;
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__IO uint32_t CHNL_PRIORITY_SET;
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__O uint32_t CHNL_PRIORITY_CLR;
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uint32_t RESERVE0[3];
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__IO uint32_t ERR_CLR; /* 0x4C */
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uint32_t RESERVE1[12];
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__IO uint32_t CHNL_IRQ_STATUS; /* 0x80 */
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__IO uint32_t IRQ_ERR_ENABLE;
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__IO uint32_t CHNL_IRQ_ENABLE;
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} LPC_DMA_TypeDef;
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/*@}*/ /* end of group LPC122x_DMA */
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/*------------- Comparator (CMP) --------------------------------*/
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/** @addtogroup LPC122x_CMD LPC122x Comparator
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@{
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*/
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typedef struct
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{
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__IO uint32_t CMP;
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__IO uint32_t VLAD;
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} LPC_COMP_TypeDef;
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/*@}*/ /* end of group LPC122x_CMD */
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/*------------- Real Timer Clock (RTC) --------------------------*/
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/** @addtogroup LPC122x_RTC LPC122x Real-time Clock
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@{
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*/
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typedef struct
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{
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__I uint32_t DR;
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__IO uint32_t MR;
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__IO uint32_t LR;
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__IO uint32_t CR;
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__IO uint32_t IMSC;
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__I uint32_t IRS;
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__I uint32_t MIS;
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__IO uint32_t ICR;
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} LPC_RTC_TypeDef;
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/*@}*/ /* end of group LPC122x_RTC */
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/*------------- Power Management Unit (PMU) --------------------------*/
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/** @addtogroup LPC122x_PMU LPC122x Power Management Unit
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@{
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*/
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typedef struct
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{
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__IO uint32_t PCON;
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__IO uint32_t GPREG0;
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__IO uint32_t GPREG1;
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__IO uint32_t GPREG2;
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__IO uint32_t GPREG3;
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__IO uint32_t GPREG4;
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} LPC_PMU_TypeDef;
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/*@}*/ /* end of group LPC122x_PMU */
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/*------------- General Purpose Input/Output (GPIO) --------------------------*/
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/** @addtogroup LPC122x_GPIO LPC122x General Purpose Input/Output
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@{
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*/
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typedef struct
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{
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__IO uint32_t MASK;
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__I uint32_t PIN;
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__IO uint32_t OUT;
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__O uint32_t SET;
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__O uint32_t CLR;
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__O uint32_t NOT;
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uint32_t RESERVE[2];
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__IO uint32_t DIR;
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__IO uint32_t IS;
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__IO uint32_t IBE;
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__IO uint32_t IEV;
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__IO uint32_t IE;
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__I uint32_t RIS;
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__I uint32_t MIS;
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__O uint32_t IC;
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} LPC_GPIO_TypeDef;
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/*@}*/ /* end of group LPC122x_GPIO */
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/*------------- Timer (TMR) --------------------------------------------------*/
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/** @addtogroup LPC122x_TMR LPC122x 16/32-bit Counter/Timer
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@{
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*/
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typedef struct
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{
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__IO uint32_t IR;
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__IO uint32_t TCR;
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__IO uint32_t TC;
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__IO uint32_t PR;
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__IO uint32_t PC;
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__IO uint32_t MCR;
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__IO uint32_t MR0;
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__IO uint32_t MR1;
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__IO uint32_t MR2;
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__IO uint32_t MR3;
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__IO uint32_t CCR;
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__I uint32_t CR0;
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__I uint32_t CR1;
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__I uint32_t CR2;
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__I uint32_t CR3;
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__IO uint32_t EMR;
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uint32_t RESERVED2[12];
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__IO uint32_t CTCR;
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__IO uint32_t PWMC;
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} LPC_TMR_TypeDef;
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/*@}*/ /* end of group LPC122x_TMR */
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/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
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/** @addtogroup LPC122x_UART LPC122x Universal Asynchronous Receiver/Transmitter
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@{
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*/
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typedef struct
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{
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union {
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__I uint32_t RBR;
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__O uint32_t THR;
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__IO uint32_t DLL;
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};
|
|
union {
|
|
__IO uint32_t DLM;
|
|
__IO uint32_t IER;
|
|
};
|
|
union {
|
|
__I uint32_t IIR;
|
|
__O uint32_t FCR;
|
|
};
|
|
__IO uint32_t LCR;
|
|
__IO uint32_t MCR;
|
|
__I uint32_t LSR;
|
|
__I uint32_t MSR;
|
|
__IO uint32_t SCR;
|
|
__IO uint32_t ACR;
|
|
__IO uint32_t ICR;
|
|
__IO uint32_t FDR;
|
|
uint32_t RESERVED0;
|
|
__IO uint32_t TER;
|
|
uint32_t RESERVED1[6];
|
|
__IO uint32_t RS485CTRL;
|
|
__IO uint32_t ADRMATCH;
|
|
__IO uint32_t RS485DLY;
|
|
__I uint32_t FIFOLVL;
|
|
} LPC_UART_TypeDef;
|
|
/*@}*/ /* end of group LPC122x_UART */
|
|
|
|
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
|
|
/** @addtogroup LPC122x_SSP LPC122x Synchronous Serial Port
|
|
@{
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR0;
|
|
__IO uint32_t CR1;
|
|
__IO uint32_t DR;
|
|
__I uint32_t SR;
|
|
__IO uint32_t CPSR;
|
|
__IO uint32_t IMSC;
|
|
__IO uint32_t RIS;
|
|
__IO uint32_t MIS;
|
|
__IO uint32_t ICR;
|
|
} LPC_SSP_TypeDef;
|
|
/*@}*/ /* end of group LPC122x_SSP */
|
|
|
|
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
|
|
/** @addtogroup LPC122x_I2C LPC122x I2C-Bus Interface
|
|
@{
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CONSET;
|
|
__I uint32_t STAT;
|
|
__IO uint32_t DAT;
|
|
__IO uint32_t ADR0;
|
|
__IO uint32_t SCLH;
|
|
__IO uint32_t SCLL;
|
|
__O uint32_t CONCLR;
|
|
__IO uint32_t MMCTRL;
|
|
__IO uint32_t ADR1;
|
|
__IO uint32_t ADR2;
|
|
__IO uint32_t ADR3;
|
|
__I uint32_t DATA_BUFFER;
|
|
__IO uint32_t MASK0;
|
|
__IO uint32_t MASK1;
|
|
__IO uint32_t MASK2;
|
|
__IO uint32_t MASK3;
|
|
} LPC_I2C_TypeDef;
|
|
/*@}*/ /* end of group LPC122x_I2C */
|
|
|
|
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
|
|
/** @addtogroup LPC122x_WDT LPC122x WatchDog Timer
|
|
@{
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t MOD;
|
|
__IO uint32_t TC;
|
|
__O uint32_t FEED;
|
|
__I uint32_t TV;
|
|
__IO uint32_t CLKSEL;
|
|
__IO uint32_t WARNINT;
|
|
__IO uint32_t WINDOW;
|
|
} LPC_WDT_TypeDef;
|
|
/*@}*/ /* end of group LPC122x_WDT */
|
|
|
|
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
|
|
/** @addtogroup LPC122x_ADC LPC122x Analog-to-Digital Converter
|
|
@{
|
|
*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t CR;
|
|
__IO uint32_t GDR;
|
|
uint32_t RESERVED0;
|
|
__IO uint32_t INTEN;
|
|
__IO uint32_t DR[8];
|
|
__I uint32_t STAT;
|
|
} LPC_ADC_TypeDef;
|
|
/*@}*/ /* end of group LPC122x_ADC */
|
|
|
|
/*------------- Flash Memory Controller (FMC) -----------------------------------*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t TBCFG; /* Time Base Config register */
|
|
__IO uint32_t FINSTR; /* Flash Instruction register */
|
|
__I uint32_t INSSTA; /* Raw Instruction Status register */
|
|
__IO uint32_t INSSCLR; /* Raw Instruction Clear register */
|
|
__IO uint32_t INT_EN; /* Interrupt Enable register */
|
|
__I uint32_t INT_STA; /* Interrupt Status register */
|
|
uint32_t RESERVED0;
|
|
__IO uint32_t ADDRLAT; /* Address Latch registers */
|
|
__IO uint32_t DATALAT; /* Data Latch register */
|
|
__IO uint32_t FIMC; /* Flash Manaul Operation register */
|
|
__IO uint32_t RDCFG; /* Read Configuration register */
|
|
__IO uint32_t EPPCFG; /* Flash Programming Permission Cofig register */
|
|
__IO uint32_t EPPAA; /* Flash Programming Permission Address A register */
|
|
__IO uint32_t EPPAB; /* Flash Programming Permission Address B register */
|
|
} LPC_FMC_TypeDef;
|
|
|
|
/*------------- CRC Engine (CRC) -----------------------------------------*/
|
|
typedef struct
|
|
{
|
|
__IO uint32_t MODE;
|
|
__IO uint32_t SEED;
|
|
union {
|
|
__I uint32_t SUM;
|
|
__O uint32_t WR_DATA_DWORD;
|
|
__O uint16_t WR_DATA_WORD;
|
|
uint16_t RESERVED_WORD;
|
|
__O uint8_t WR_DATA_BYTE;
|
|
uint8_t RESERVED_BYTE[3];
|
|
};
|
|
__I uint32_t ID;
|
|
} LPC_CRC_TypeDef;
|
|
|
|
#if defined ( __CC_ARM )
|
|
#pragma no_anon_unions
|
|
#endif
|
|
|
|
/******************************************************************************/
|
|
/* Peripheral memory map */
|
|
/******************************************************************************/
|
|
/* Base addresses */
|
|
#define LPC_FLASH_BASE (0x00000000)
|
|
#define LPC_RAM_BASE (0x10000000)
|
|
#define LPC_APB0_BASE (0x40000000)
|
|
#define LPC_AHB_BASE (0x50000000)
|
|
|
|
/* APB0 peripherals */
|
|
#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
|
|
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
|
|
#define LPC_UART0_BASE (LPC_APB0_BASE + 0x08000)
|
|
#define LPC_UART1_BASE (LPC_APB0_BASE + 0x0C000)
|
|
#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x10000)
|
|
#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x14000)
|
|
#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x18000)
|
|
#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x1C000)
|
|
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x20000)
|
|
|
|
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
|
|
#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000)
|
|
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
|
|
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
|
|
#define LPC_DMA_BASE (LPC_APB0_BASE + 0x4C000)
|
|
#define LPC_RTC_BASE (LPC_APB0_BASE + 0x50000)
|
|
#define LPC_COMP_BASE (LPC_APB0_BASE + 0x54000)
|
|
|
|
/* AHB peripherals */
|
|
#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
|
|
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
|
|
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
|
|
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
|
|
#define LPC_FMC_BASE (LPC_AHB_BASE + 0x60000)
|
|
#define LPC_CRC_BASE (LPC_AHB_BASE + 0x70000)
|
|
|
|
/******************************************************************************/
|
|
/* Peripheral declaration */
|
|
/******************************************************************************/
|
|
#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
|
|
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
|
|
#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
|
|
#define LPC_UART1 ((LPC_UART_TypeDef *) LPC_UART1_BASE )
|
|
#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
|
|
#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
|
|
#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
|
|
#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
|
|
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
|
|
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
|
|
#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE )
|
|
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
|
|
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
|
|
#define LPC_DMA ((LPC_DMA_TypeDef *) LPC_DMA_BASE )
|
|
#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
|
|
#define LPC_COMP ((LPC_COMP_TypeDef *) LPC_COMP_BASE )
|
|
|
|
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
|
|
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
|
|
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
|
|
#define LPC_FMC ((LPC_FMC_TypeDef *) LPC_FMC_BASE )
|
|
#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif // __LPC122x_H__
|