913 lines
21 KiB
C
913 lines
21 KiB
C
/**************************************************************************//**
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* @file core_cmFunc.h
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* @brief CMSIS Cortex-M Core Function Access Header File
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* @version V1.40
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* @date 16. February 2010
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*
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* @note
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* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __CORE_CMFUNC_H__
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#define __CORE_CMFUNC_H__
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/* ########################### Core Function Access ########################### */
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#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
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/* ARM armcc specific functions */
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/**
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* @brief Enable IRQ Interrupts
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*
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* Enables IRQ interrupts by clearing the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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/* intrinsic void __enable_irq(); */
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/**
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* @brief Disable IRQ Interrupts
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*
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* Disables IRQ interrupts by setting the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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/* intrinsic void __disable_irq(); */
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/**
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* @brief Return the Control Register value
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*
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* @return Control value
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*
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* Return the content of the control register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_CONTROL(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Control Register value
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*
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* @param control Control value
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*
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* Set the control register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_CONTROL(uint32_t control);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get IPSR Register value
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*
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* @return uint32_t IPSR value
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*
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* return the content of the IPSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_IPSR(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get APSR Register value
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*
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* @return uint32_t APSR value
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*
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* return the content of the APSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_APSR(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Get xPSR Register value
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*
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* @return uint32_t xPSR value
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*
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* return the content of the xPSR register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_xPSR(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Process Stack Pointer
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*
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* @return ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_PSP(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param topOfProcStack Process Stack Pointer
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_PSP(uint32_t topOfProcStack);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Main Stack Pointer
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*
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* @return Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_MSP(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Main Stack Pointer
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*
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* @param topOfMainStack Main Stack Pointer
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_MSP(uint32_t topOfMainStack);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_MSP(uint32_t mainStackPointer)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = mainStackPointer;
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Priority Mask value
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*
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* @return PriMask
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*
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* Return state of the priority mask bit from the priority mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_PRIMASK(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Priority Mask value
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*
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* @param priMask PriMask
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*
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* Set the priority mask bit in the priority mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_PRIMASK(uint32_t priMask);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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#endif /* __ARMCC_VERSION */
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#if (__CORTEX_M >= 0x03)
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/**
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* @brief Enable FIQ Interrupts
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*
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* Enables FIQ interrupts by clearing the F-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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#define __enable_fault_irq __enable_fiq
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/**
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* @brief Disable FIQ Interrupts
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*
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* Disables FIQ interrupts by setting the F-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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#define __disable_fault_irq __disable_fiq
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/**
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* @brief Return the Base Priority value
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*
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* @return BasePriority
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*
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* Return the content of the base priority register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_BASEPRI(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_BASEPRI(void)
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{
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Base Priority value
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*
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* @param basePri BasePriority
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*
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* Set the base priority register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_BASEPRI(uint32_t basePri);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_BASEPRI(uint32_t basePri)
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xff);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Return the Fault Mask value
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*
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* @return FaultMask
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*
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* Return the content of the fault mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern uint32_t __get_FAULTMASK(void);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE uint32_t __get_FAULTMASK(void)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
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}
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#endif /* __ARMCC_VERSION */
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/**
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* @brief Set the Fault Mask value
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*
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* @param faultMask faultMask value
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*
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* Set the fault mask register
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*/
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#if (__ARMCC_VERSION < 400000)
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extern void __set_FAULTMASK(uint32_t faultMask);
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#else /* (__ARMCC_VERSION >= 400000) */
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static __INLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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register uint32_t __regFaultMask __ASM("faultmask");
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__regFaultMask = (faultMask & 1);
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}
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#endif /* __ARMCC_VERSION */
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#endif /* (__CORTEX_M >= 0x03) */
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#if (__CORTEX_M == 0x04)
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/**
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* @brief Return the FPSCR value
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*
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* @return FloatingPointStatusControlRegister
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*
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* Return the content of the FPSCR register
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*/
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static __INLINE uint32_t __get_FPSCR(void)
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{
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#if (__FPU_PRESENT == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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return(__regfpscr);
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#else
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return(0);
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#endif
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}
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/**
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* @brief Set the FPSCR value
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*
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* @param fpscr FloatingPointStatusControlRegister
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*
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* Set the FPSCR register
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*/
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static __INLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if (__FPU_PRESENT == 1)
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register uint32_t __regfpscr __ASM("fpscr");
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__regfpscr = (fpscr);
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#endif
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}
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#endif /* (__CORTEX_M == 0x04) */
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#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
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/* IAR iccarm specific functions */
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#if defined (__ICCARM__)
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#include <intrinsics.h> /* IAR Intrinsics */
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#endif
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#pragma diag_suppress=Pe940
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/**
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* @brief Enable IRQ Interrupts
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*
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* Enables IRQ interrupts by clearing the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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#define __enable_irq __enable_interrupt
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/**
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* @brief Disable IRQ Interrupts
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*
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* Disables IRQ interrupts by setting the I-bit in the CPSR.
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* Can only be executed in Privileged modes.
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*/
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#define __disable_irq __disable_interrupt
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/**
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* @brief Return the Control Register value
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*
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* @return Control value
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*
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* Return the content of the control register
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*/
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/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
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/**
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* @brief Set the Control Register value
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*
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* @param control Control value
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*
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* Set the control register
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*/
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/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
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/**
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* @brief Get IPSR Register value
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*
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* @return uint32_t IPSR value
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*
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* return the content of the IPSR register
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*/
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static uint32_t __get_IPSR(void)
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{
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__ASM("mrs r0, ipsr");
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}
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/**
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* @brief Get APSR Register value
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*
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* @return uint32_t APSR value
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*
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* return the content of the APSR register
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*/
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/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */
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/**
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* @brief Get xPSR Register value
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*
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* @return uint32_t xPSR value
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*
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* return the content of the xPSR register
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*/
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static uint32_t __get_xPSR(void)
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{
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__ASM("mrs r0, psr"); // assembler does not know "xpsr"
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}
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/**
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* @brief Return the Process Stack Pointer
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*
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* @return ProcessStackPointer
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*
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* Return the actual process stack pointer
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*/
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static uint32_t __get_PSP(void)
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{
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__ASM("mrs r0, psp");
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}
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/**
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* @brief Set the Process Stack Pointer
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*
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* @param topOfProcStack Process Stack Pointer
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*
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* Assign the value ProcessStackPointer to the MSP
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* (process stack pointer) Cortex processor register
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*/
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static void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM("msr psp, r0");
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}
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/**
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* @brief Return the Main Stack Pointer
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|
*
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* @return Main Stack Pointer
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*
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* Return the current value of the MSP (main stack pointer)
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* Cortex processor register
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*/
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static uint32_t __get_MSP(void)
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{
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__ASM("mrs r0, msp");
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}
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/**
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* @brief Set the Main Stack Pointer
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|
*
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* @param topOfMainStack Main Stack Pointer
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*
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* Assign the value mainStackPointer to the MSP
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* (main stack pointer) Cortex processor register
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|
*/
|
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static void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM("msr msp, r0");
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}
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|
|
|
/**
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|
* @brief Return the Priority Mask value
|
|
*
|
|
* @return PriMask
|
|
*
|
|
* Return state of the priority mask bit from the priority mask register
|
|
*/
|
|
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
|
|
|
|
/**
|
|
* @brief Set the Priority Mask value
|
|
*
|
|
* @param priMask PriMask
|
|
*
|
|
* Set the priority mask bit in the priority mask register
|
|
*/
|
|
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
|
|
|
|
|
|
#if (__CORTEX_M >= 0x03)
|
|
|
|
/**
|
|
* @brief Enable FIQ Interrupts
|
|
*
|
|
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
|
* Can only be executed in Privileged modes.
|
|
*/
|
|
static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
|
|
|
|
/**
|
|
* @brief Disable FIQ Interrupts
|
|
*
|
|
* Disables FIQ interrupts by setting the F-bit in the CPSR.
|
|
* Can only be executed in Privileged modes.
|
|
*/
|
|
static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
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|
|
|
/**
|
|
* @brief Return the Base Priority value
|
|
*
|
|
* @return BasePriority
|
|
*
|
|
* Return the content of the base priority register
|
|
*/
|
|
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
|
|
|
|
/**
|
|
* @brief Set the Base Priority value
|
|
*
|
|
* @param basePri BasePriority
|
|
*
|
|
* Set the base priority register
|
|
*/
|
|
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
|
|
|
|
/**
|
|
* @brief Return the Fault Mask value
|
|
*
|
|
* @return FaultMask
|
|
*
|
|
* Return the content of the fault mask register
|
|
*/
|
|
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
|
|
|
|
/**
|
|
* @brief Set the Fault Mask value
|
|
*
|
|
* @param faultMask faultMask value
|
|
*
|
|
* Set the fault mask register
|
|
*/
|
|
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
|
|
|
|
#endif /* (__CORTEX_M >= 0x03) */
|
|
|
|
|
|
#if (__CORTEX_M == 0x04)
|
|
|
|
/**
|
|
* @brief Return the FPSCR value
|
|
*
|
|
* @return FloatingPointStatusControlRegister
|
|
*
|
|
* Return the content of the FPSCR register
|
|
*/
|
|
static __INLINE uint32_t __get_FPSCR(void)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
/* not yet implemented */
|
|
return(0);
|
|
#else
|
|
return(0);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief Set the FPSCR value
|
|
*
|
|
* @param fpscr FloatingPointStatusControlRegister
|
|
*
|
|
* Set the FPSCR register
|
|
*/
|
|
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
/* not yet implemented */
|
|
#endif
|
|
}
|
|
|
|
#endif /* (__CORTEX_M == 0x04) */
|
|
|
|
#pragma diag_default=Pe940
|
|
|
|
|
|
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
|
|
/* GNU gcc specific functions */
|
|
/**
|
|
* @brief Enable IRQ Interrupts
|
|
*
|
|
* Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
|
* Can only be executed in Privileged modes.
|
|
*/
|
|
static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
|
|
|
|
/**
|
|
* @brief Disable IRQ Interrupts
|
|
*
|
|
* Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
* Can only be executed in Privileged modes.
|
|
*/
|
|
static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
|
|
|
|
/**
|
|
* @brief Return the Control Register value
|
|
*
|
|
* @return Control value
|
|
*
|
|
* Return the content of the control register
|
|
*/
|
|
static __INLINE uint32_t __get_CONTROL(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the Control Register value
|
|
*
|
|
* @param control Control value
|
|
*
|
|
* Set the control register
|
|
*/
|
|
static __INLINE void __set_CONTROL(uint32_t control)
|
|
{
|
|
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
|
}
|
|
|
|
/**
|
|
* @brief Get IPSR Register value
|
|
*
|
|
* @return uint32_t IPSR value
|
|
*
|
|
* return the content of the IPSR register
|
|
*/
|
|
static __INLINE uint32_t __get_IPSR(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Get APSR Register value
|
|
*
|
|
* @return uint32_t APSR value
|
|
*
|
|
* return the content of the APSR register
|
|
*/
|
|
static __INLINE uint32_t __get_APSR(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Get xPSR Register value
|
|
*
|
|
* @return uint32_t xPSR value
|
|
*
|
|
* return the content of the xPSR register
|
|
*/
|
|
static __INLINE uint32_t __get_xPSR(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Return the Process Stack Pointer
|
|
*
|
|
* @return ProcessStackPointer
|
|
*
|
|
* Return the actual process stack pointer
|
|
*/
|
|
static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) );
|
|
static __INLINE uint32_t __get_PSP(void)
|
|
{
|
|
register uint32_t result __ASM ("r0") = 0;
|
|
|
|
__ASM volatile ("MRS %0, psp\n"
|
|
"BX lr \n" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the Process Stack Pointer
|
|
*
|
|
* @param topOfProcStack Process Stack Pointer
|
|
*
|
|
* Assign the value ProcessStackPointer to the MSP
|
|
* (process stack pointer) Cortex processor register
|
|
*/
|
|
static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
|
|
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
|
{
|
|
__ASM volatile ("MSR psp, %0\n"
|
|
"BX lr \n" : : "r" (topOfProcStack) );
|
|
}
|
|
|
|
/**
|
|
* @brief Return the Main Stack Pointer
|
|
*
|
|
* @return Main Stack Pointer
|
|
*
|
|
* Return the current value of the MSP (main stack pointer)
|
|
* Cortex processor register
|
|
*/
|
|
static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) );
|
|
static __INLINE uint32_t __get_MSP(void)
|
|
{
|
|
register uint32_t result __ASM ("r0") = 0;
|
|
|
|
__ASM volatile ("MRS %0, msp\n"
|
|
"BX lr \n" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the Main Stack Pointer
|
|
*
|
|
* @param topOfMainStack Main Stack Pointer
|
|
*
|
|
* Assign the value mainStackPointer to the MSP
|
|
* (main stack pointer) Cortex processor register
|
|
*/
|
|
static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
|
|
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
|
{
|
|
__ASM volatile ("MSR msp, %0\n"
|
|
"BX lr \n" : : "r" (topOfMainStack) );
|
|
}
|
|
|
|
/**
|
|
* @brief Return the Priority Mask value
|
|
*
|
|
* @return PriMask
|
|
*
|
|
* Return state of the priority mask bit from the priority mask register
|
|
*/
|
|
static __INLINE uint32_t __get_PRIMASK(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the Priority Mask value
|
|
*
|
|
* @param priMask PriMask
|
|
*
|
|
* Set the priority mask bit in the priority mask register
|
|
*/
|
|
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
|
{
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
|
}
|
|
|
|
|
|
#if (__CORTEX_M >= 0x03)
|
|
|
|
/**
|
|
* @brief Enable FIQ Interrupts
|
|
*
|
|
* Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
|
* Can only be executed in Privileged modes.
|
|
*/
|
|
static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
|
|
|
|
/**
|
|
* @brief Disable FIQ Interrupts
|
|
*
|
|
* Disables FIQ interrupts by setting the F-bit in the CPSR.
|
|
* Can only be executed in Privileged modes.
|
|
*/
|
|
static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
|
|
|
|
/**
|
|
* @brief Return the Base Priority value
|
|
*
|
|
* @return BasePriority
|
|
*
|
|
* Return the content of the base priority register
|
|
*/
|
|
static __INLINE uint32_t __get_BASEPRI(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
/**
|
|
* @brief Set the Base Priority value
|
|
*
|
|
* @param basePri BasePriority
|
|
*
|
|
* Set the base priority register
|
|
*/
|
|
static __INLINE void __set_BASEPRI(uint32_t value)
|
|
{
|
|
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
|
}
|
|
|
|
/**
|
|
* @brief Return the Fault Mask value
|
|
*
|
|
* @return FaultMask
|
|
*
|
|
* Return the content of the fault mask register
|
|
*/
|
|
static __INLINE uint32_t __get_FAULTMASK(void)
|
|
{
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
|
return(result);
|
|
}
|
|
|
|
#endif /* (__CORTEX_M >= 0x03) */
|
|
|
|
/**
|
|
* @brief Set the Fault Mask value
|
|
*
|
|
* @param faultMask faultMask value
|
|
*
|
|
* Set the fault mask register
|
|
*/
|
|
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
|
{
|
|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
|
}
|
|
|
|
|
|
#if (__CORTEX_M == 0x04)
|
|
|
|
/**
|
|
* @brief Return the FPSCR value
|
|
*
|
|
* @return FloatingPointStatusControlRegister
|
|
*
|
|
* Return the content of the FPSCR register
|
|
*/
|
|
static __INLINE uint32_t __get_FPSCR(void)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
uint32_t result=0;
|
|
|
|
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
|
|
return(result);
|
|
#else
|
|
return(0);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief Set the FPSCR value
|
|
*
|
|
* @param fpscr FloatingPointStatusControlRegister
|
|
*
|
|
* Set the FPSCR register
|
|
*/
|
|
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
|
{
|
|
#if (__FPU_PRESENT == 1)
|
|
__ASM volatile ("MSR control, %0" : : "r" (fpscr) );
|
|
#endif
|
|
}
|
|
|
|
#endif /* (__CORTEX_M == 0x04) */
|
|
|
|
|
|
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
|
|
/* TASKING carm specific functions */
|
|
|
|
/*
|
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
|
* Including the CMSIS ones.
|
|
*/
|
|
|
|
#endif
|
|
|
|
#endif // __CORE_CMFUNC_H__
|