165 lines
4.1 KiB
C
165 lines
4.1 KiB
C
/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#include "fh_def.h"
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#include "fh_arch.h"
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#include "inc/fh_driverlib.h"
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void SPI_EnableSlaveen(struct fh_spi_obj *spi_obj, rt_uint32_t port)
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{
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rt_uint32_t reg;
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reg = GET_REG(spi_obj->base + OFFSET_SPI_SER);
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reg |= (1 << port);
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SET_REG(spi_obj->base + OFFSET_SPI_SER, reg);
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}
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void SPI_DisableSlaveen(struct fh_spi_obj *spi_obj, rt_uint32_t port)
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{
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rt_uint32_t reg;
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reg = GET_REG(spi_obj->base + OFFSET_SPI_SER);
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reg &= ~(1 << port);
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SET_REG(spi_obj->base + OFFSET_SPI_SER, reg);
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}
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void SPI_SetTxLevel(struct fh_spi_obj *spi_obj, rt_uint32_t level)
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{
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SET_REG(spi_obj->base + OFFSET_SPI_TXFTLR, level);
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}
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void SPI_EnableInterrupt(struct fh_spi_obj *spi_obj, rt_uint32_t flag)
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{
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rt_uint32_t reg;
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reg = GET_REG(spi_obj->base + OFFSET_SPI_IMR);
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reg |= flag;
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SET_REG(spi_obj->base + OFFSET_SPI_IMR, reg);
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}
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void SPI_EnableDma(struct fh_spi_obj *spi_obj, rt_uint32_t channel)
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{
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rt_uint32_t reg;
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reg = GET_REG(spi_obj->base + OFFSET_SPI_DMACTRL);
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reg |= channel;
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SET_REG(spi_obj->base + OFFSET_SPI_DMACTRL, reg);
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}
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void SPI_DisableDma(struct fh_spi_obj *spi_obj, rt_uint32_t channel)
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{
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rt_uint32_t reg;
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reg = GET_REG(spi_obj->base + OFFSET_SPI_DMACTRL);
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reg &= ~channel;
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SET_REG(spi_obj->base + OFFSET_SPI_DMACTRL, reg);
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}
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void SPI_DisableInterrupt(struct fh_spi_obj *spi_obj, rt_uint32_t flag)
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{
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rt_uint32_t reg;
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reg = GET_REG(spi_obj->base + OFFSET_SPI_IMR);
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reg &= ~flag;
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SET_REG(spi_obj->base + OFFSET_SPI_IMR, reg);
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}
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rt_uint32_t SPI_InterruptStatus(struct fh_spi_obj *spi_obj)
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{
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return GET_REG(spi_obj->base + OFFSET_SPI_ISR);
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}
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void SPI_ClearInterrupt(struct fh_spi_obj *spi_obj)
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{
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GET_REG(spi_obj->base + OFFSET_SPI_ICR);
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}
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rt_uint32_t SPI_ReadTxFifoLevel(struct fh_spi_obj *spi_obj)
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{
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return GET_REG(spi_obj->base + OFFSET_SPI_TXFLR);
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}
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rt_uint32_t SPI_ReadRxFifoLevel(struct fh_spi_obj *spi_obj)
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{
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return GET_REG(spi_obj->base + OFFSET_SPI_RXFLR);
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}
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UINT8 SPI_ReadData(struct fh_spi_obj *spi_obj)
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{
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return GET_REG(spi_obj->base + OFFSET_SPI_DR) & 0xff;
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}
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void SPI_WriteData(struct fh_spi_obj *spi_obj, UINT8 data)
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{
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SET_REG(spi_obj->base + OFFSET_SPI_DR, data);
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}
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rt_uint32_t SPI_ReadStatus(struct fh_spi_obj *spi_obj)
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{
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return GET_REG(spi_obj->base + OFFSET_SPI_SR);
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}
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void SPI_Enable(struct fh_spi_obj *spi_obj, int enable)
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{
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SET_REG(spi_obj->base + OFFSET_SPI_SSIENR, enable);
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}
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void SPI_WriteTxDmaLevel(struct fh_spi_obj *spi_obj, rt_uint32_t data)
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{
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SET_REG(spi_obj->base + OFFSET_SPI_DMATDL, data);
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}
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void SPI_WriteRxDmaLevel(struct fh_spi_obj *spi_obj, rt_uint32_t data)
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{
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SET_REG(spi_obj->base + OFFSET_SPI_DMARDL, data);
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}
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void SPI_SetParameter(struct fh_spi_obj *spi_obj)
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{
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rt_uint32_t reg;
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struct spi_config *config;
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config = &spi_obj->config;
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SET_REG(spi_obj->base + OFFSET_SPI_BAUD, config->clk_div);
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reg = GET_REG(spi_obj->base + OFFSET_SPI_CTRL0);
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reg &= ~(0x3ff);
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reg |= config->data_size \
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| config->frame_format \
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| config->clk_phase \
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| config->clk_polarity \
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| config->transfer_mode;
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SET_REG(spi_obj->base + OFFSET_SPI_CTRL0, reg);
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}
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