402 lines
14 KiB
C
402 lines
14 KiB
C
/*
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* File : rthw.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "synopsys_emac.h"
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/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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extern EMAC_DMADESCTypeDef *DMATxDescToSet;
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extern EMAC_DMADESCTypeDef *DMARxDescToGet;
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/**
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* Initializes the ETHERNET peripheral according to the specified
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*/
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rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
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{
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rt_uint32_t value = 0;
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/*-------------------------------- MAC Config ------------------------------*/
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/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
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/* Get the ETHERNET MACMIIAR value */
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value = ETHERNET_MAC->GAR;
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/* Clear CSR Clock Range CR[2:0] bits */
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value &= MACMIIAR_CR_MASK;
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/* Get hclk frequency value */
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/* Set CR bits depending on hclk value */
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if((SystemCoreClock >= 20000000)&&(SystemCoreClock < 35000000))
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{
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/* CSR Clock Range between 20-35 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div16;
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}
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else if((SystemCoreClock >= 35000000)&&(SystemCoreClock < 60000000))
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{
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/* CSR Clock Range between 35-60 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div26;
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}
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else if((SystemCoreClock >= 60000000)&&(SystemCoreClock <= 100000000))
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{
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/* CSR Clock Range between 60-100 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div42;
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}
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else if((SystemCoreClock >= 100000000)&&(SystemCoreClock <= 150000000))
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{
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/* CSR Clock Range between 100-150 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div62;
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}
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else if((SystemCoreClock >= 150000000)&&(SystemCoreClock <= 250000000))
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{
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/* CSR Clock Range between 150-250 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div102;
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}
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else /* if((SystemCoreClock >= 250000000)&&(SystemCoreClock <= 300000000)) */
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{
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/* CSR Clock Range between 250-300 MHz */
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value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div122;
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}
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/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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ETHERNET_MAC->GAR = (rt_uint32_t)value;
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/*------------------------ ETHERNET MACCR Configuration --------------------*/
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/* Get the ETHERNET MACCR value */
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value = ETHERNET_MAC->MCR;
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/* Clear WD, PCE, PS, TE and RE bits */
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value &= MACCR_CLEAR_MASK;
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value |= (rt_uint32_t)(EMAC_Watchdog_Enable |
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EMAC_Jabber_Enable |
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EMAC_InterFrameGap_96Bit |
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EMAC_CarrierSense_Enable |
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EMAC_Speed_100M |
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EMAC_ReceiveOwn_Enable |
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EMAC_LoopbackMode_Disable |
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EMAC_Mode_FullDuplex |
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EMAC_ChecksumOffload_Enable |
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EMAC_RetryTransmission_Disable |
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EMAC_AutomaticPadCRCStrip_Disable |
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EMAC_BackOffLimit_10 |
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EMAC_DeferralCheck_Disable);
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/* Write to ETHERNET MACCR */
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value |= (1<<15);
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value &= ~(1<<25);
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value &= ~(1<<24);
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ETHERNET_MAC->MCR = (rt_uint32_t)value;
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/*----------------------- ETHERNET MACFFR Configuration --------------------*/
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/* Write to ETHERNET MACFFR */
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ETHERNET_MAC->MFFR = (rt_uint32_t)(EMAC_ReceiveAll_Enable |
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EMAC_SourceAddrFilter_Disable |
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EMAC_PassControlFrames_BlockAll |
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EMAC_BroadcastFramesReception_Disable |
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EMAC_DestinationAddrFilter_Normal |
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EMAC_PromiscuousMode_Disable |
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EMAC_MulticastFramesFilter_Perfect |
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EMAC_UnicastFramesFilter_Perfect);
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/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
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/* Write to ETHERNET MACHTHR */
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ETHERNET_MAC->MHTRH = 0;
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/* Write to ETHERNET MACHTLR */
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ETHERNET_MAC->MHTRL = 0;
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/*----------------------- ETHERNET MACFCR Configuration --------------------*/
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/* Get the ETHERNET MACFCR value */
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value = ETHERNET_MAC->FCR;
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/* Clear xx bits */
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value &= MACFCR_CLEAR_MASK;
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value |= (rt_uint32_t)((0 << 16) |
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EMAC_ZeroQuantaPause_Disable |
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EMAC_PauseLowThreshold_Minus4 |
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EMAC_UnicastPauseFrameDetect_Disable |
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EMAC_ReceiveFlowControl_Disable |
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EMAC_TransmitFlowControl_Disable);
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/* Write to ETHERNET MACFCR */
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ETHERNET_MAC->FCR = (rt_uint32_t)value;
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/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
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ETHERNET_MAC->VTR = (rt_uint32_t)(EMAC_VLANTagComparison_16Bit |
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0);
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/*-------------------------------- DMA Config ------------------------------*/
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/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
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/* Get the ETHERNET DMAOMR value */
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value = ETHERNET_MAC->OMR;
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/* Clear xx bits */
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value &= DMAOMR_CLEAR_MASK;
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value |= (rt_uint32_t)(EMAC_DropTCPIPChecksumErrorFrame_Disable |
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EMAC_ReceiveStoreForward_Enable |
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EMAC_FlushReceivedFrame_Enable |
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EMAC_TransmitStoreForward_Enable |
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EMAC_TransmitThresholdControl_64Bytes |
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EMAC_ForwardErrorFrames_Disable |
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EMAC_ForwardUndersizedGoodFrames_Disable |
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EMAC_ReceiveThresholdControl_64Bytes |
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EMAC_SecondFrameOperate_Disable);
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/* Write to ETHERNET DMAOMR */
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ETHERNET_MAC->OMR = (rt_uint32_t)value;
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/*----------------------- ETHERNET DMABMR Configuration --------------------*/
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ETHERNET_MAC->BMR = (rt_uint32_t)(EMAC_AddressAlignedBeats_Enable |
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EMAC_FixedBurst_Enable |
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EMAC_RxDMABurstLength_32Beat | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
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EMAC_TxDMABurstLength_32Beat |
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(0 << 2) |
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EMAC_DMAArbitration_RoundRobin_RxTx_2_1 |
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EMAC_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
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/* Return Ethernet configuration success */
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return EMAC_SUCCESS;
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}
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/**
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* Enables or disables the specified ETHERNET DMA interrupts.
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*/
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void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the selected ETHERNET DMA interrupts */
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ETHERNET_MAC->IER |= EMAC_DMA_IT;
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}
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else
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{
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/* Disable the selected ETHERNET DMA interrupts */
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ETHERNET_MAC->IER &=(~(rt_uint32_t)EMAC_DMA_IT);
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}
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}
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/**
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* Configures the selected MAC address.
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*/
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void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr)
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{
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rt_uint32_t value;
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/* Calculate the selectecd MAC address high register */
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value = ((rt_uint32_t)Addr[5] << 8) | (rt_uint32_t)Addr[4];
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/* Load the selectecd MAC address high register */
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//(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_HBASE + MacAddr)) = value;
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ETHERNET_MAC->MARs[MacAddr].MARH = value;
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/* Calculate the selectecd MAC address low register */
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value = ((rt_uint32_t)Addr[3] << 24) | ((rt_uint32_t)Addr[2] << 16) | ((rt_uint32_t)Addr[1] << 8) | Addr[0];
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/* Load the selectecd MAC address low register */
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//(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_LBASE + MacAddr)) = value;
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ETHERNET_MAC->MARs[MacAddr].MARL = value;
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}
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/**
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* Enables or disables the MAC transmission.
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*/
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void EMAC_MACTransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the MAC transmission */
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ETHERNET_MAC->MCR |= EMAC_MACCR_TE;
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}
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else
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{
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/* Disable the MAC transmission */
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ETHERNET_MAC->MCR &= ~EMAC_MACCR_TE;
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}
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}
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/**
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* Clears the ETHERNET transmit FIFO.
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*/
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void EMAC_FlushTransmitFIFO(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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/* Set the Flush Transmit FIFO bit */
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ETHERNET_MAC->OMR |= EMAC_DMAOMR_FTF;
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}
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/**
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* Enables or disables the MAC reception.
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*/
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void EMAC_MACReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the MAC reception */
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ETHERNET_MAC->MCR |= EMAC_MACCR_RE;
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}
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else
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{
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/* Disable the MAC reception */
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ETHERNET_MAC->MCR &= ~EMAC_MACCR_RE;
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}
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}
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/**
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* Enables or disables the DMA transmission.
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*/
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void EMAC_DMATransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the DMA transmission */
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ETHERNET_MAC->OMR |= EMAC_DMAOMR_ST;
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}
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else
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{
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/* Disable the DMA transmission */
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ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_ST;
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}
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}
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/**
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* Enables or disables the DMA reception.
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*/
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void EMAC_DMAReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
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{
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if (NewState)
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{
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/* Enable the DMA reception */
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ETHERNET_MAC->OMR |= EMAC_DMAOMR_SR;
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}
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else
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{
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/* Disable the DMA reception */
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ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_SR;
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}
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}
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/**
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* Enables ENET MAC and DMA reception/transmission
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*/
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void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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/* Enable transmit state machine of the MAC for transmission on the MII */
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EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
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/* Flush Transmit FIFO */
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EMAC_FlushTransmitFIFO(ETHERNET_MAC);
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/* Enable receive state machine of the MAC for reception from the MII */
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EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
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/* Start DMA transmission */
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EMAC_DMATransmissionCmd(ETHERNET_MAC, RT_TRUE);
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/* Start DMA reception */
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EMAC_DMAReceptionCmd(ETHERNET_MAC, RT_TRUE);
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}
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/**
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* Clears the ETHERNET's DMA interrupt pending bit.
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*/
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void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t pending)
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{
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/* Clear the selected ETHERNET DMA IT */
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ETHERNET_MAC->SR = (rt_uint32_t) pending;
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}
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/**
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* Resumes the DMA Transmission by writing to the DmaRxPollDemand register
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* (the data written could be anything). This forces the DMA to resume reception.
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*/
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void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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ETHERNET_MAC->RPDR = 0;
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}
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/**
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* Resumes the DMA Transmission by writing to the DmaTxPollDemand register
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* (the data written could be anything). This forces the DMA to resume transmission.
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*/
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void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC)
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{
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ETHERNET_MAC->TPDR = 0;
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}
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/**
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* Read a PHY register
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*/
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rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg)
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{
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rt_uint32_t value = 0;
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volatile rt_uint32_t timeout = 0;
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/* Get the ETHERNET MACMIIAR value */
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value = ETHERNET_MAC->GAR;
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/* Keep only the CSR Clock Range CR[2:0] bits value */
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value &= ~MACMIIAR_CR_MASK;
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/* Prepare the MII address register value */
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value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
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value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */
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value &= ~EMAC_MACMIIAR_MW; /* Set the read mode */
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value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */
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/* Write the result value into the MII Address register */
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ETHERNET_MAC->GAR = value;
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/* Check for the Busy flag */
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do
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{
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timeout++;
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value = ETHERNET_MAC->GAR;
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}
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while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_READ_TO));
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/* Return ERROR in case of timeout */
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if(timeout == PHY_READ_TO)
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{
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return (rt_uint16_t)EMAC_ERROR;
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}
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/* Return data register value */
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return (rt_uint16_t)(ETHERNET_MAC->GDR);
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}
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/**
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* Write to a PHY register
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*/
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rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue)
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{
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rt_uint32_t value = 0;
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volatile rt_uint32_t timeout = 0;
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/* Get the ETHERNET MACMIIAR value */
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value = ETHERNET_MAC->GAR;
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/* Keep only the CSR Clock Range CR[2:0] bits value */
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value &= ~MACMIIAR_CR_MASK;
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/* Prepare the MII register address value */
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value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
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value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */
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value |= EMAC_MACMIIAR_MW; /* Set the write mode */
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value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */
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/* Give the value to the MII data register */
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ETHERNET_MAC->GDR = PHYValue;
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/* Write the result value into the MII Address register */
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ETHERNET_MAC->GAR = value;
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/* Check for the Busy flag */
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do
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{
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timeout++;
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value = ETHERNET_MAC->GAR;
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}
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while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_WRITE_TO));
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/* Return ERROR in case of timeout */
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if(timeout == PHY_WRITE_TO)
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{
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return EMAC_ERROR;
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}
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/* Return SUCCESS */
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return EMAC_SUCCESS;
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}
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