115 lines
4.7 KiB
C
115 lines
4.7 KiB
C
/*
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* @brief CCAN registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CCAN_001_H_
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#define __CCAN_001_H_
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#include "sys_config.h"
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup IP_CCAN_001 IP: CCAN register block and driver
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* @ingroup IP_Drivers
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* @{
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*/
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/**
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* @brief CCAN Controller Area Network register block structure
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*/
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typedef struct { /*!< C_CAN Structure */
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__IO uint32_t CNTL; /*!< CAN control */
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__IO uint32_t STAT; /*!< Status register */
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__I uint32_t EC; /*!< Error counter */
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__IO uint32_t BT; /*!< Bit timing register */
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__I uint32_t INT; /*!< Interrupt register */
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__IO uint32_t TEST; /*!< Test register */
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__IO uint32_t BRPE; /*!< Baud rate prescaler extension register */
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__I uint32_t RESERVED0;
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__IO uint32_t IF1_CMDREQ; /*!< Message interface command request */
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union {
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__IO uint32_t IF1_CMDMSK_R; /*!< Message interface command mask (read direction) */
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__IO uint32_t IF1_CMDMSK_W; /*!< Message interface command mask (write direction) */
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};
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__IO uint32_t IF1_MSK1; /*!< Message interface mask 1 */
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__IO uint32_t IF1_MSK2; /*!< Message interface 1 mask 2 */
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__IO uint32_t IF1_ARB1; /*!< Message interface 1 arbitration 1 */
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__IO uint32_t IF1_ARB2; /*!< Message interface 1 arbitration 2 */
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__IO uint32_t IF1_MCTRL; /*!< Message interface 1 message control */
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__IO uint32_t IF1_DA1; /*!< Message interface data A1 */
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__IO uint32_t IF1_DA2; /*!< Message interface 1 data A2 */
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__IO uint32_t IF1_DB1; /*!< Message interface 1 data B1 */
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__IO uint32_t IF1_DB2; /*!< Message interface 1 data B2 */
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__I uint32_t RESERVED1[13];
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__IO uint32_t IF2_CMDREQ; /*!< Message interface command request */
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union {
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__IO uint32_t IF2_CMDMSK_R; /*!< Message interface command mask (read direction) */
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__IO uint32_t IF2_CMDMSK_W; /*!< Message interface command mask (write direction) */
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};
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__IO uint32_t IF2_MSK1; /*!< Message interface mask 1 */
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__IO uint32_t IF2_MSK2; /*!< Message interface 1 mask 2 */
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__IO uint32_t IF2_ARB1; /*!< Message interface 1 arbitration 1 */
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__IO uint32_t IF2_ARB2; /*!< Message interface 1 arbitration 2 */
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__IO uint32_t IF2_MCTRL; /*!< Message interface 1 message control */
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__IO uint32_t IF2_DA1; /*!< Message interface data A1 */
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__IO uint32_t IF2_DA2; /*!< Message interface 1 data A2 */
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__IO uint32_t IF2_DB1; /*!< Message interface 1 data B1 */
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__IO uint32_t IF2_DB2; /*!< Message interface 1 data B2 */
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__I uint32_t RESERVED2[21];
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__I uint32_t TXREQ1; /*!< Transmission request 1 */
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__I uint32_t TXREQ2; /*!< Transmission request 2 */
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__I uint32_t RESERVED3[6];
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__I uint32_t ND1; /*!< New data 1 */
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__I uint32_t ND2; /*!< New data 2 */
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__I uint32_t RESERVED4[6];
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__I uint32_t IR1; /*!< Interrupt pending 1 */
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__I uint32_t IR2; /*!< Interrupt pending 2 */
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__I uint32_t RESERVED5[6];
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__I uint32_t MSGV1; /*!< Message valid 1 */
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__I uint32_t MSGV2; /*!< Message valid 2 */
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__I uint32_t RESERVED6[6];
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__IO uint32_t CLKDIV; /*!< CAN clock divider register */
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} IP_CCAN_001_Type;
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CCAN_001_H_ */
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