775 lines
31 KiB
ArmAsm
775 lines
31 KiB
ArmAsm
;/*****************************************************************************
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; * @file: startup_MK60F12.s
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; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
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; * MK60F12
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; * @version: 1.1
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; * @date: 2011-11-3
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; *
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; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_DMA16_IRQHandler ; DMA channel 0/16 transfer complete interrupt
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DCD DMA1_DMA17_IRQHandler ; DMA channel 1/17 transfer complete interrupt
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DCD DMA2_DMA18_IRQHandler ; DMA channel 2/18 transfer complete interrupt
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DCD DMA3_DMA19_IRQHandler ; DMA channel 3/19 transfer complete interrupt
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DCD DMA4_DMA20_IRQHandler ; DMA channel 4/20 transfer complete interrupt
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DCD DMA5_DMA21_IRQHandler ; DMA channel 5/21 transfer complete interrupt
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DCD DMA6_DMA22_IRQHandler ; DMA channel 6/22 transfer complete interrupt
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DCD DMA7_DMA23_IRQHandler ; DMA channel 7/23 transfer complete interrupt
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DCD DMA8_DMA24_IRQHandler ; DMA channel 8/24 transfer complete interrupt
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DCD DMA9_DMA25_IRQHandler ; DMA channel 9/25 transfer complete interrupt
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DCD DMA10_DMA26_IRQHandler ; DMA channel 10/26 transfer complete interrupt
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DCD DMA11_DMA27_IRQHandler ; DMA channel 11/27 transfer complete interrupt
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DCD DMA12_DMA28_IRQHandler ; DMA channel 12/28 transfer complete interrupt
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DCD DMA13_DMA29_IRQHandler ; DMA channel 13/29 transfer complete interrupt
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DCD DMA14_DMA30_IRQHandler ; DMA channel 14/30 transfer complete interrupt
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DCD DMA15_DMA31_IRQHandler ; DMA channel 15/31 transfer complete interrupt
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DCD DMA_Error_IRQHandler ; DMA error interrupt
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DCD MCM_IRQHandler ; Normal interrupt
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DCD FTFE_IRQHandler ; FTFE interrupt
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DCD Read_Collision_IRQHandler ; Read collision interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD Watchdog_IRQHandler ; WDOG interrupt
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DCD RNG_IRQHandler ; RNGB interrupt
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD I2C1_IRQHandler ; I2C1 interrupt
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD SPI1_IRQHandler ; SPI1 interrupt
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DCD SPI2_IRQHandler ; SPI2 interrupt
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DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
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DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
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DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
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DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
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DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
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DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
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DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
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DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
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DCD CAN1_ORed_Message_buffer_IRQHandler ; CAN1 OR'd message buffers interrupt
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DCD CAN1_Bus_Off_IRQHandler ; CAN1 bus off interrupt
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DCD CAN1_Error_IRQHandler ; CAN1 error interrupt
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DCD CAN1_Tx_Warning_IRQHandler ; CAN1 Tx warning interrupt
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DCD CAN1_Rx_Warning_IRQHandler ; CAN1 Rx warning interrupt
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DCD CAN1_Wake_Up_IRQHandler ; CAN1 wake up interrupt
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DCD Reserved59_IRQHandler ; Reserved interrupt 59
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DCD UART0_LON_IRQHandler ; UART0 LON interrupt
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DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
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DCD UART0_ERR_IRQHandler ; UART0 error interrupt
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DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
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DCD UART1_ERR_IRQHandler ; UART1 error interrupt
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DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
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DCD UART2_ERR_IRQHandler ; UART2 error interrupt
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DCD UART3_RX_TX_IRQHandler ; UART3 receive/transmit interrupt
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DCD UART3_ERR_IRQHandler ; UART3 error interrupt
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DCD UART4_RX_TX_IRQHandler ; UART4 receive/transmit interrupt
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DCD UART4_ERR_IRQHandler ; UART4 error interrupt
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DCD UART5_RX_TX_IRQHandler ; UART5 receive/transmit interrupt
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DCD UART5_ERR_IRQHandler ; UART5 error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD ADC1_IRQHandler ; ADC1 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD CMP1_IRQHandler ; CMP1 interrupt
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DCD CMP2_IRQHandler ; CMP2 interrupt
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DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
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DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
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DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
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DCD CMT_IRQHandler ; CMT interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
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DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
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DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
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DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
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DCD PDB0_IRQHandler ; PDB0 interrupt
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DCD USB0_IRQHandler ; USB0 interrupt
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DCD USBDCD_IRQHandler ; USBDCD interrupt
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DCD ENET_1588_Timer_IRQHandler ; Ethernet MAC IEEE 1588 timer interrupt
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DCD ENET_Transmit_IRQHandler ; Ethernet MAC transmit interrupt
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DCD ENET_Receive_IRQHandler ; Ethernet MAC receive interrupt
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DCD ENET_Error_IRQHandler ; Ethernet MAC error and miscelaneous interrupt
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DCD Reserved95_IRQHandler ; Reserved interrupt 95
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DCD SDHC_IRQHandler ; SDHC interrupt
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DCD DAC0_IRQHandler ; DAC0 interrupt
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DCD DAC1_IRQHandler ; DAC1 interrupt
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DCD TSI0_IRQHandler ; TSI0 interrupt
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DCD MCG_IRQHandler ; MCG interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD Reserved102_IRQHandler ; Reserved interrupt 102
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTB_IRQHandler ; Port B interrupt
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DCD PORTC_IRQHandler ; Port C interrupt
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DCD PORTD_IRQHandler ; Port D interrupt
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DCD PORTE_IRQHandler ; Port E interrupt
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DCD PORTF_IRQHandler ; Port F interrupt
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DCD Reserved109_IRQHandler ; Reserved interrupt 109
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DCD SWI_IRQHandler ; Software interrupt
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DCD NFC_IRQHandler ; NAND flash controller interrupt
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DCD USBHS_IRQHandler ; USB high speed OTG interrupt
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DCD Reserved113_IRQHandler ; Reserved interrupt 113
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DCD CMP3_IRQHandler ; CMP3 interrupt
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DCD Reserved115_IRQHandler ; Reserved interrupt 115
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DCD Reserved116_IRQHandler ; Reserved interrupt 116
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DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
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DCD ADC2_IRQHandler ; ADC2 interrupt
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DCD ADC3_IRQHandler ; ADC3 interrupt
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DCD I2S1_Tx_IRQHandler ; I2S1 transmit interrupt
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DCD I2S1_Rx_IRQHandler ; I2S1 receive interrupt
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DCD DefaultISR ; 122
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DCD DefaultISR ; 123
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DCD DefaultISR ; 124
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DCD DefaultISR ; 125
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DCD DefaultISR ; 126
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DCD DefaultISR ; 127
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DCD DefaultISR ; 128
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DCD DefaultISR ; 129
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DCD DefaultISR ; 130
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DCD DefaultISR ; 131
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DCD DefaultISR ; 132
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DCD DefaultISR ; 133
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DCD DefaultISR ; 134
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DCD DefaultISR ; 135
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DCD DefaultISR ; 136
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DCD DefaultISR ; 137
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DCD DefaultISR ; 138
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DCD DefaultISR ; 139
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DCD DefaultISR ; 140
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DCD DefaultISR ; 141
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DCD DefaultISR ; 142
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DCD DefaultISR ; 143
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DCD DefaultISR ; 144
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DCD DefaultISR ; 145
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DCD DefaultISR ; 146
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DCD DefaultISR ; 147
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DCD DefaultISR ; 148
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DCD DefaultISR ; 149
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DCD DefaultISR ; 150
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DCD DefaultISR ; 151
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DCD DefaultISR ; 152
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DCD DefaultISR ; 153
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DCD DefaultISR ; 154
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DCD DefaultISR ; 155
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DCD DefaultISR ; 156
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DCD DefaultISR ; 157
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DCD DefaultISR ; 158
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DCD DefaultISR ; 159
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DCD DefaultISR ; 160
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DCD DefaultISR ; 161
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DCD DefaultISR ; 162
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DCD DefaultISR ; 163
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DCD DefaultISR ; 164
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DCD DefaultISR ; 165
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DCD DefaultISR ; 166
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DCD DefaultISR ; 167
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DCD DefaultISR ; 168
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DCD DefaultISR ; 169
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DCD DefaultISR ; 170
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DCD DefaultISR ; 171
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DCD DefaultISR ; 172
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DCD DefaultISR ; 173
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DCD DefaultISR ; 174
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DCD DefaultISR ; 175
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DCD DefaultISR ; 176
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DCD DefaultISR ; 177
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DCD DefaultISR ; 178
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DCD DefaultISR ; 179
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DCD DefaultISR ; 180
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DCD DefaultISR ; 181
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DCD DefaultISR ; 182
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DCD DefaultISR ; 183
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DCD DefaultISR ; 184
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DCD DefaultISR ; 185
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DCD DefaultISR ; 186
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DCD DefaultISR ; 187
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DCD DefaultISR ; 188
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DCD DefaultISR ; 189
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DCD DefaultISR ; 190
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DCD DefaultISR ; 191
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DCD DefaultISR ; 192
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DCD DefaultISR ; 193
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DCD DefaultISR ; 194
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DCD DefaultISR ; 195
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DCD DefaultISR ; 196
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DCD DefaultISR ; 197
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DCD DefaultISR ; 198
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DCD DefaultISR ; 199
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DCD DefaultISR ; 200
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DCD DefaultISR ; 201
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DCD DefaultISR ; 202
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DCD DefaultISR ; 203
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DCD DefaultISR ; 204
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DCD DefaultISR ; 205
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DCD DefaultISR ; 206
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DCD DefaultISR ; 207
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DCD DefaultISR ; 208
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DCD DefaultISR ; 209
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DCD DefaultISR ; 210
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DCD DefaultISR ; 211
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DCD DefaultISR ; 212
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DCD DefaultISR ; 213
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DCD DefaultISR ; 214
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DCD DefaultISR ; 215
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DCD DefaultISR ; 216
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DCD DefaultISR ; 217
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DCD DefaultISR ; 218
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DCD DefaultISR ; 219
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DCD DefaultISR ; 220
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DCD DefaultISR ; 221
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DCD DefaultISR ; 222
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DCD DefaultISR ; 223
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DCD DefaultISR ; 224
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DCD DefaultISR ; 225
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DCD DefaultISR ; 226
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DCD DefaultISR ; 227
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DCD DefaultISR ; 228
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DCD DefaultISR ; 229
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DCD DefaultISR ; 230
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DCD DefaultISR ; 231
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DCD DefaultISR ; 232
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DCD DefaultISR ; 233
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DCD DefaultISR ; 234
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DCD DefaultISR ; 235
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DCD DefaultISR ; 236
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DCD DefaultISR ; 237
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DCD DefaultISR ; 238
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DCD DefaultISR ; 239
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DCD DefaultISR ; 240
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DCD DefaultISR ; 241
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DCD DefaultISR ; 242
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DCD DefaultISR ; 243
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DCD DefaultISR ; 244
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DCD DefaultISR ; 245
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DCD DefaultISR ; 246
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DCD DefaultISR ; 247
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DCD DefaultISR ; 248
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DCD DefaultISR ; 249
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DCD DefaultISR ; 250
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DCD DefaultISR ; 251
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DCD DefaultISR ; 252
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DCD DefaultISR ; 253
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DCD DefaultISR ; 254
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DCD DefaultISR ; 255
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; <h> Data flash protection byte (FDPROT)
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; <i> Each bit protects a 1/8 region of the data flash memory.
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; <i> (Program flash only devices: Reserved)
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; <o.0> FDPROT.0
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; <o.1> FDPROT.1
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; <o.2> FDPROT.2
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; <o.3> FDPROT.3
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; <o.4> FDPROT.4
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; <o.5> FDPROT.5
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; <o.6> FDPROT.6
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; <o.7> FDPROT.7
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nFDPROT EQU 0x00
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FDPROT EQU nFDPROT:EOR:0xFF
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; </h>
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; <h> EEPROM protection byte (FEPROT)
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; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
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; <i> (Program flash only devices: Reserved)
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; <o.0> FEPROT.0
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; <o.1> FEPROT.1
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; <o.2> FEPROT.2
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; <o.3> FEPROT.3
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; <o.4> FEPROT.4
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; <o.5> FEPROT.5
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; <o.6> FEPROT.6
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; <o.7> FEPROT.7
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nFEPROT EQU 0x00
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FEPROT EQU nFEPROT:EOR:0xFF
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT
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; <0=> Low-power boot
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; <1=> normal boot
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; <o.1> EZPORT_DIS
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; <0=> EzPort operation is enabled
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; <1=> EzPort operation is disabled
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <i> This bits define the security state of the MCU.
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <i> This bits define the security state of the MCU.
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <i> Mass Erase Enable Bits
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; <i> Enables and disables mass erase capability of the FTFL module
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor key Security Enable
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; <i> These bits enable and disable backdoor key access to the FTFL module.
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FSEC EQU 0xFE
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; </h>
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, FEPROT, FDPROT
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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|
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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|
BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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|
|
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NMI_Handler PROC
|
|
EXPORT NMI_Handler [WEAK]
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B .
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|
ENDP
|
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HardFault_Handler\
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PROC
|
|
EXPORT HardFault_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
MemManage_Handler\
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|
PROC
|
|
EXPORT MemManage_Handler [WEAK]
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|
B .
|
|
ENDP
|
|
BusFault_Handler\
|
|
PROC
|
|
EXPORT BusFault_Handler [WEAK]
|
|
B .
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|
ENDP
|
|
UsageFault_Handler\
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PROC
|
|
EXPORT UsageFault_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
SVC_Handler PROC
|
|
EXPORT SVC_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
DebugMon_Handler\
|
|
PROC
|
|
EXPORT DebugMon_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
PendSV_Handler PROC
|
|
EXPORT PendSV_Handler [WEAK]
|
|
B .
|
|
ENDP
|
|
SysTick_Handler PROC
|
|
EXPORT SysTick_Handler [WEAK]
|
|
B .
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ENDP
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|
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Default_Handler PROC
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EXPORT DMA0_DMA16_IRQHandler [WEAK]
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EXPORT DMA1_DMA17_IRQHandler [WEAK]
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EXPORT DMA2_DMA18_IRQHandler [WEAK]
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EXPORT DMA3_DMA19_IRQHandler [WEAK]
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EXPORT DMA4_DMA20_IRQHandler [WEAK]
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EXPORT DMA5_DMA21_IRQHandler [WEAK]
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EXPORT DMA6_DMA22_IRQHandler [WEAK]
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EXPORT DMA7_DMA23_IRQHandler [WEAK]
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|
EXPORT DMA8_DMA24_IRQHandler [WEAK]
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|
EXPORT DMA9_DMA25_IRQHandler [WEAK]
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EXPORT DMA10_DMA26_IRQHandler [WEAK]
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EXPORT DMA11_DMA27_IRQHandler [WEAK]
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EXPORT DMA12_DMA28_IRQHandler [WEAK]
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EXPORT DMA13_DMA29_IRQHandler [WEAK]
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EXPORT DMA14_DMA30_IRQHandler [WEAK]
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EXPORT DMA15_DMA31_IRQHandler [WEAK]
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EXPORT DMA_Error_IRQHandler [WEAK]
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EXPORT MCM_IRQHandler [WEAK]
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EXPORT FTFE_IRQHandler [WEAK]
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EXPORT Read_Collision_IRQHandler [WEAK]
|
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EXPORT LVD_LVW_IRQHandler [WEAK]
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EXPORT LLW_IRQHandler [WEAK]
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EXPORT Watchdog_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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|
EXPORT SPI1_IRQHandler [WEAK]
|
|
EXPORT SPI2_IRQHandler [WEAK]
|
|
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
|
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EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
|
|
EXPORT CAN0_Error_IRQHandler [WEAK]
|
|
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
|
|
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
|
|
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
|
|
EXPORT I2S0_Tx_IRQHandler [WEAK]
|
|
EXPORT I2S0_Rx_IRQHandler [WEAK]
|
|
EXPORT CAN1_ORed_Message_buffer_IRQHandler [WEAK]
|
|
EXPORT CAN1_Bus_Off_IRQHandler [WEAK]
|
|
EXPORT CAN1_Error_IRQHandler [WEAK]
|
|
EXPORT CAN1_Tx_Warning_IRQHandler [WEAK]
|
|
EXPORT CAN1_Rx_Warning_IRQHandler [WEAK]
|
|
EXPORT CAN1_Wake_Up_IRQHandler [WEAK]
|
|
EXPORT Reserved59_IRQHandler [WEAK]
|
|
EXPORT UART0_LON_IRQHandler [WEAK]
|
|
EXPORT UART0_RX_TX_IRQHandler [WEAK]
|
|
EXPORT UART0_ERR_IRQHandler [WEAK]
|
|
EXPORT UART1_RX_TX_IRQHandler [WEAK]
|
|
EXPORT UART1_ERR_IRQHandler [WEAK]
|
|
EXPORT UART2_RX_TX_IRQHandler [WEAK]
|
|
EXPORT UART2_ERR_IRQHandler [WEAK]
|
|
EXPORT UART3_RX_TX_IRQHandler [WEAK]
|
|
EXPORT UART3_ERR_IRQHandler [WEAK]
|
|
EXPORT UART4_RX_TX_IRQHandler [WEAK]
|
|
EXPORT UART4_ERR_IRQHandler [WEAK]
|
|
EXPORT UART5_RX_TX_IRQHandler [WEAK]
|
|
EXPORT UART5_ERR_IRQHandler [WEAK]
|
|
EXPORT ADC0_IRQHandler [WEAK]
|
|
EXPORT ADC1_IRQHandler [WEAK]
|
|
EXPORT CMP0_IRQHandler [WEAK]
|
|
EXPORT CMP1_IRQHandler [WEAK]
|
|
EXPORT CMP2_IRQHandler [WEAK]
|
|
EXPORT FTM0_IRQHandler [WEAK]
|
|
EXPORT FTM1_IRQHandler [WEAK]
|
|
EXPORT FTM2_IRQHandler [WEAK]
|
|
EXPORT CMT_IRQHandler [WEAK]
|
|
EXPORT RTC_IRQHandler [WEAK]
|
|
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
|
EXPORT PIT0_IRQHandler [WEAK]
|
|
EXPORT PIT1_IRQHandler [WEAK]
|
|
EXPORT PIT2_IRQHandler [WEAK]
|
|
EXPORT PIT3_IRQHandler [WEAK]
|
|
EXPORT PDB0_IRQHandler [WEAK]
|
|
EXPORT USB0_IRQHandler [WEAK]
|
|
EXPORT USBDCD_IRQHandler [WEAK]
|
|
EXPORT ENET_1588_Timer_IRQHandler [WEAK]
|
|
EXPORT ENET_Transmit_IRQHandler [WEAK]
|
|
EXPORT ENET_Receive_IRQHandler [WEAK]
|
|
EXPORT ENET_Error_IRQHandler [WEAK]
|
|
EXPORT Reserved95_IRQHandler [WEAK]
|
|
EXPORT SDHC_IRQHandler [WEAK]
|
|
EXPORT DAC0_IRQHandler [WEAK]
|
|
EXPORT DAC1_IRQHandler [WEAK]
|
|
EXPORT TSI0_IRQHandler [WEAK]
|
|
EXPORT MCG_IRQHandler [WEAK]
|
|
EXPORT LPTimer_IRQHandler [WEAK]
|
|
EXPORT Reserved102_IRQHandler [WEAK]
|
|
EXPORT PORTA_IRQHandler [WEAK]
|
|
EXPORT PORTB_IRQHandler [WEAK]
|
|
EXPORT PORTC_IRQHandler [WEAK]
|
|
EXPORT PORTD_IRQHandler [WEAK]
|
|
EXPORT PORTE_IRQHandler [WEAK]
|
|
EXPORT PORTF_IRQHandler [WEAK]
|
|
EXPORT Reserved109_IRQHandler [WEAK]
|
|
EXPORT SWI_IRQHandler [WEAK]
|
|
EXPORT NFC_IRQHandler [WEAK]
|
|
EXPORT USBHS_IRQHandler [WEAK]
|
|
EXPORT Reserved113_IRQHandler [WEAK]
|
|
EXPORT CMP3_IRQHandler [WEAK]
|
|
EXPORT Reserved115_IRQHandler [WEAK]
|
|
EXPORT Reserved116_IRQHandler [WEAK]
|
|
EXPORT FTM3_IRQHandler [WEAK]
|
|
EXPORT ADC2_IRQHandler [WEAK]
|
|
EXPORT ADC3_IRQHandler [WEAK]
|
|
EXPORT I2S1_Tx_IRQHandler [WEAK]
|
|
EXPORT I2S1_Rx_IRQHandler [WEAK]
|
|
EXPORT DefaultISR [WEAK]
|
|
|
|
DMA0_DMA16_IRQHandler
|
|
DMA1_DMA17_IRQHandler
|
|
DMA2_DMA18_IRQHandler
|
|
DMA3_DMA19_IRQHandler
|
|
DMA4_DMA20_IRQHandler
|
|
DMA5_DMA21_IRQHandler
|
|
DMA6_DMA22_IRQHandler
|
|
DMA7_DMA23_IRQHandler
|
|
DMA8_DMA24_IRQHandler
|
|
DMA9_DMA25_IRQHandler
|
|
DMA10_DMA26_IRQHandler
|
|
DMA11_DMA27_IRQHandler
|
|
DMA12_DMA28_IRQHandler
|
|
DMA13_DMA29_IRQHandler
|
|
DMA14_DMA30_IRQHandler
|
|
DMA15_DMA31_IRQHandler
|
|
DMA_Error_IRQHandler
|
|
MCM_IRQHandler
|
|
FTFE_IRQHandler
|
|
Read_Collision_IRQHandler
|
|
LVD_LVW_IRQHandler
|
|
LLW_IRQHandler
|
|
Watchdog_IRQHandler
|
|
RNG_IRQHandler
|
|
I2C0_IRQHandler
|
|
I2C1_IRQHandler
|
|
SPI0_IRQHandler
|
|
SPI1_IRQHandler
|
|
SPI2_IRQHandler
|
|
CAN0_ORed_Message_buffer_IRQHandler
|
|
CAN0_Bus_Off_IRQHandler
|
|
CAN0_Error_IRQHandler
|
|
CAN0_Tx_Warning_IRQHandler
|
|
CAN0_Rx_Warning_IRQHandler
|
|
CAN0_Wake_Up_IRQHandler
|
|
I2S0_Tx_IRQHandler
|
|
I2S0_Rx_IRQHandler
|
|
CAN1_ORed_Message_buffer_IRQHandler
|
|
CAN1_Bus_Off_IRQHandler
|
|
CAN1_Error_IRQHandler
|
|
CAN1_Tx_Warning_IRQHandler
|
|
CAN1_Rx_Warning_IRQHandler
|
|
CAN1_Wake_Up_IRQHandler
|
|
Reserved59_IRQHandler
|
|
UART0_LON_IRQHandler
|
|
UART0_RX_TX_IRQHandler
|
|
UART0_ERR_IRQHandler
|
|
UART1_RX_TX_IRQHandler
|
|
UART1_ERR_IRQHandler
|
|
UART2_RX_TX_IRQHandler
|
|
UART2_ERR_IRQHandler
|
|
UART3_RX_TX_IRQHandler
|
|
UART3_ERR_IRQHandler
|
|
UART4_RX_TX_IRQHandler
|
|
UART4_ERR_IRQHandler
|
|
UART5_RX_TX_IRQHandler
|
|
UART5_ERR_IRQHandler
|
|
ADC0_IRQHandler
|
|
ADC1_IRQHandler
|
|
CMP0_IRQHandler
|
|
CMP1_IRQHandler
|
|
CMP2_IRQHandler
|
|
FTM0_IRQHandler
|
|
FTM1_IRQHandler
|
|
FTM2_IRQHandler
|
|
CMT_IRQHandler
|
|
RTC_IRQHandler
|
|
RTC_Seconds_IRQHandler
|
|
PIT0_IRQHandler
|
|
PIT1_IRQHandler
|
|
PIT2_IRQHandler
|
|
PIT3_IRQHandler
|
|
PDB0_IRQHandler
|
|
USB0_IRQHandler
|
|
USBDCD_IRQHandler
|
|
ENET_1588_Timer_IRQHandler
|
|
ENET_Transmit_IRQHandler
|
|
ENET_Receive_IRQHandler
|
|
ENET_Error_IRQHandler
|
|
Reserved95_IRQHandler
|
|
SDHC_IRQHandler
|
|
DAC0_IRQHandler
|
|
DAC1_IRQHandler
|
|
TSI0_IRQHandler
|
|
MCG_IRQHandler
|
|
LPTimer_IRQHandler
|
|
Reserved102_IRQHandler
|
|
PORTA_IRQHandler
|
|
PORTB_IRQHandler
|
|
PORTC_IRQHandler
|
|
PORTD_IRQHandler
|
|
PORTE_IRQHandler
|
|
PORTF_IRQHandler
|
|
Reserved109_IRQHandler
|
|
SWI_IRQHandler
|
|
NFC_IRQHandler
|
|
USBHS_IRQHandler
|
|
Reserved113_IRQHandler
|
|
CMP3_IRQHandler
|
|
Reserved115_IRQHandler
|
|
Reserved116_IRQHandler
|
|
FTM3_IRQHandler
|
|
ADC2_IRQHandler
|
|
ADC3_IRQHandler
|
|
I2S1_Tx_IRQHandler
|
|
I2S1_Rx_IRQHandler
|
|
DefaultISR
|
|
|
|
B .
|
|
|
|
ENDP
|
|
|
|
|
|
ALIGN
|
|
|
|
|
|
; User Initial Stack & Heap
|
|
|
|
IF :DEF:__MICROLIB
|
|
|
|
EXPORT __initial_sp
|
|
EXPORT __heap_base
|
|
EXPORT __heap_limit
|
|
|
|
ELSE
|
|
|
|
IMPORT __use_two_region_memory
|
|
EXPORT __user_initial_stackheap
|
|
__user_initial_stackheap
|
|
|
|
LDR R0, = Heap_Mem
|
|
LDR R1, =(Stack_Mem + Stack_Size)
|
|
LDR R2, = (Heap_Mem + Heap_Size)
|
|
LDR R3, = Stack_Mem
|
|
BX LR
|
|
|
|
ALIGN
|
|
|
|
ENDIF
|
|
|
|
|
|
END
|