994 lines
43 KiB
C
994 lines
43 KiB
C
/*
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** ###################################################################
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** Version: rev. 0.1, 2017-01-10
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** Build: b171017
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**
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** Abstract:
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** Chip specific module features.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** Redistribution and use in source and binary forms, with or without modification,
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** are permitted provided that the following conditions are met:
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**
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** 1. Redistributions of source code must retain the above copyright notice, this list
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** of conditions and the following disclaimer.
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**
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** 2. Redistributions in binary form must reproduce the above copyright notice, this
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** list of conditions and the following disclaimer in the documentation and/or
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** other materials provided with the distribution.
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**
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** 3. Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from this
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** software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 0.1 (2017-01-10)
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** Initial version.
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**
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** ###################################################################
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*/
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#ifndef _MIMXRT1052_FEATURES_H_
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#define _MIMXRT1052_FEATURES_H_
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/* SOC module features */
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/* @brief ACMP availability on the SoC. */
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#define FSL_FEATURE_SOC_ACMP_COUNT (0)
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/* @brief ADC availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC_COUNT (2)
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/* @brief ADC12 availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC12_COUNT (0)
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/* @brief ADC16 availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC16_COUNT (0)
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/* @brief ADC_5HC availability on the SoC. */
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#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
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/* @brief AES availability on the SoC. */
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#define FSL_FEATURE_SOC_AES_COUNT (0)
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/* @brief AFE availability on the SoC. */
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#define FSL_FEATURE_SOC_AFE_COUNT (0)
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/* @brief AGC availability on the SoC. */
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#define FSL_FEATURE_SOC_AGC_COUNT (0)
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/* @brief AIPS availability on the SoC. */
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#define FSL_FEATURE_SOC_AIPS_COUNT (0)
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/* @brief AIPSTZ availability on the SoC. */
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#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
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/* @brief ANATOP availability on the SoC. */
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#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
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/* @brief AOI availability on the SoC. */
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#define FSL_FEATURE_SOC_AOI_COUNT (2)
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/* @brief APBH availability on the SoC. */
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#define FSL_FEATURE_SOC_APBH_COUNT (0)
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/* @brief ASMC availability on the SoC. */
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#define FSL_FEATURE_SOC_ASMC_COUNT (0)
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/* @brief ASRC availability on the SoC. */
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#define FSL_FEATURE_SOC_ASRC_COUNT (0)
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/* @brief ASYNC_SYSCON availability on the SoC. */
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#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0)
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/* @brief ATX availability on the SoC. */
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#define FSL_FEATURE_SOC_ATX_COUNT (0)
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/* @brief AXBS availability on the SoC. */
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#define FSL_FEATURE_SOC_AXBS_COUNT (0)
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/* @brief BCH availability on the SoC. */
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#define FSL_FEATURE_SOC_BCH_COUNT (0)
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/* @brief BLEDP availability on the SoC. */
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#define FSL_FEATURE_SOC_BLEDP_COUNT (0)
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/* @brief BOD availability on the SoC. */
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#define FSL_FEATURE_SOC_BOD_COUNT (0)
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/* @brief CAAM availability on the SoC. */
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#define FSL_FEATURE_SOC_CAAM_COUNT (0)
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/* @brief CADC availability on the SoC. */
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#define FSL_FEATURE_SOC_CADC_COUNT (0)
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/* @brief CALIB availability on the SoC. */
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#define FSL_FEATURE_SOC_CALIB_COUNT (0)
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/* @brief CAN availability on the SoC. */
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#define FSL_FEATURE_SOC_CAN_COUNT (0)
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/* @brief CAU availability on the SoC. */
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#define FSL_FEATURE_SOC_CAU_COUNT (0)
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/* @brief CAU3 availability on the SoC. */
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#define FSL_FEATURE_SOC_CAU3_COUNT (0)
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/* @brief CCM availability on the SoC. */
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#define FSL_FEATURE_SOC_CCM_COUNT (1)
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/* @brief CCM_ANALOG availability on the SoC. */
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#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
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/* @brief CHRG availability on the SoC. */
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#define FSL_FEATURE_SOC_CHRG_COUNT (0)
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/* @brief CLKCTL0 availability on the SoC. */
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#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0)
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/* @brief CLKCTL1 availability on the SoC. */
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#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0)
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/* @brief CMP availability on the SoC. */
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#define FSL_FEATURE_SOC_CMP_COUNT (4)
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/* @brief CMT availability on the SoC. */
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#define FSL_FEATURE_SOC_CMT_COUNT (0)
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/* @brief CNC availability on the SoC. */
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#define FSL_FEATURE_SOC_CNC_COUNT (0)
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/* @brief COP availability on the SoC. */
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#define FSL_FEATURE_SOC_COP_COUNT (0)
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/* @brief CRC availability on the SoC. */
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#define FSL_FEATURE_SOC_CRC_COUNT (0)
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/* @brief CS availability on the SoC. */
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#define FSL_FEATURE_SOC_CS_COUNT (0)
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/* @brief CSI availability on the SoC. */
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#define FSL_FEATURE_SOC_CSI_COUNT (1)
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/* @brief CT32B availability on the SoC. */
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#define FSL_FEATURE_SOC_CT32B_COUNT (0)
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/* @brief CTI availability on the SoC. */
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#define FSL_FEATURE_SOC_CTI_COUNT (0)
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/* @brief CTIMER availability on the SoC. */
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#define FSL_FEATURE_SOC_CTIMER_COUNT (0)
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/* @brief DAC availability on the SoC. */
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#define FSL_FEATURE_SOC_DAC_COUNT (0)
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/* @brief DAC32 availability on the SoC. */
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#define FSL_FEATURE_SOC_DAC32_COUNT (0)
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/* @brief DCDC availability on the SoC. */
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#define FSL_FEATURE_SOC_DCDC_COUNT (1)
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/* @brief DCP availability on the SoC. */
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#define FSL_FEATURE_SOC_DCP_COUNT (1)
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/* @brief DDR availability on the SoC. */
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#define FSL_FEATURE_SOC_DDR_COUNT (0)
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/* @brief DDRC availability on the SoC. */
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#define FSL_FEATURE_SOC_DDRC_COUNT (0)
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/* @brief DDRC_MP availability on the SoC. */
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#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
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/* @brief DDR_PHY availability on the SoC. */
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#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
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/* @brief DMA availability on the SoC. */
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#define FSL_FEATURE_SOC_DMA_COUNT (0)
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/* @brief DMAMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
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/* @brief DMIC availability on the SoC. */
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#define FSL_FEATURE_SOC_DMIC_COUNT (0)
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/* @brief DRY availability on the SoC. */
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#define FSL_FEATURE_SOC_DRY_COUNT (0)
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/* @brief DSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_DSPI_COUNT (0)
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/* @brief ECSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
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/* @brief EDMA availability on the SoC. */
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#define FSL_FEATURE_SOC_EDMA_COUNT (1)
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/* @brief EEPROM availability on the SoC. */
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#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
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/* @brief EIM availability on the SoC. */
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#define FSL_FEATURE_SOC_EIM_COUNT (0)
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/* @brief EMC availability on the SoC. */
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#define FSL_FEATURE_SOC_EMC_COUNT (0)
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/* @brief EMVSIM availability on the SoC. */
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#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
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/* @brief ENC availability on the SoC. */
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#define FSL_FEATURE_SOC_ENC_COUNT (4)
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/* @brief ENET availability on the SoC. */
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#define FSL_FEATURE_SOC_ENET_COUNT (1)
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/* @brief EPDC availability on the SoC. */
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#define FSL_FEATURE_SOC_EPDC_COUNT (0)
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/* @brief EPIT availability on the SoC. */
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#define FSL_FEATURE_SOC_EPIT_COUNT (0)
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/* @brief ESAI availability on the SoC. */
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#define FSL_FEATURE_SOC_ESAI_COUNT (0)
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/* @brief EWM availability on the SoC. */
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#define FSL_FEATURE_SOC_EWM_COUNT (1)
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/* @brief FB availability on the SoC. */
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#define FSL_FEATURE_SOC_FB_COUNT (0)
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/* @brief FGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
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/* @brief FLASH availability on the SoC. */
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#define FSL_FEATURE_SOC_FLASH_COUNT (0)
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/* @brief FLEXCAN availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
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/* @brief FLEXCOMM availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
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/* @brief FLEXIO availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
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/* @brief FLEXRAM availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
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/* @brief FLEXSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
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/* @brief FMC availability on the SoC. */
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#define FSL_FEATURE_SOC_FMC_COUNT (0)
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/* @brief FREQME availability on the SoC. */
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#define FSL_FEATURE_SOC_FREQME_COUNT (0)
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/* @brief FSKDT availability on the SoC. */
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#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
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/* @brief FSP availability on the SoC. */
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#define FSL_FEATURE_SOC_FSP_COUNT (0)
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/* @brief FTFA availability on the SoC. */
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#define FSL_FEATURE_SOC_FTFA_COUNT (0)
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/* @brief FTFE availability on the SoC. */
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#define FSL_FEATURE_SOC_FTFE_COUNT (0)
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/* @brief FTFL availability on the SoC. */
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#define FSL_FEATURE_SOC_FTFL_COUNT (0)
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/* @brief FTM availability on the SoC. */
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#define FSL_FEATURE_SOC_FTM_COUNT (0)
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/* @brief FTMRA availability on the SoC. */
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#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
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/* @brief FTMRE availability on the SoC. */
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#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
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/* @brief FTMRH availability on the SoC. */
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#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
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/* @brief GINT availability on the SoC. */
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#define FSL_FEATURE_SOC_GINT_COUNT (0)
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/* @brief GPC availability on the SoC. */
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#define FSL_FEATURE_SOC_GPC_COUNT (1)
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/* @brief GPC_PGC availability on the SoC. */
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#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
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/* @brief GPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_GPIO_COUNT (0)
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/* @brief GPMI availability on the SoC. */
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#define FSL_FEATURE_SOC_GPMI_COUNT (0)
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/* @brief GPT availability on the SoC. */
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#define FSL_FEATURE_SOC_GPT_COUNT (2)
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/* @brief HASH availability on the SoC. */
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#define FSL_FEATURE_SOC_HASH_COUNT (0)
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/* @brief HSADC availability on the SoC. */
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#define FSL_FEATURE_SOC_HSADC_COUNT (0)
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/* @brief I2C availability on the SoC. */
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#define FSL_FEATURE_SOC_I2C_COUNT (0)
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/* @brief I2S availability on the SoC. */
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#define FSL_FEATURE_SOC_I2S_COUNT (3)
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/* @brief ICS availability on the SoC. */
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#define FSL_FEATURE_SOC_ICS_COUNT (0)
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/* @brief IEE availability on the SoC. */
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#define FSL_FEATURE_SOC_IEE_COUNT (0)
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/* @brief IEER availability on the SoC. */
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#define FSL_FEATURE_SOC_IEER_COUNT (0)
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/* @brief IGPIO availability on the SoC. */
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#define FSL_FEATURE_SOC_IGPIO_COUNT (5)
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/* @brief II2C availability on the SoC. */
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#define FSL_FEATURE_SOC_II2C_COUNT (0)
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/* @brief INPUTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0)
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/* @brief INTMUX availability on the SoC. */
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#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
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/* @brief IOCON availability on the SoC. */
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#define FSL_FEATURE_SOC_IOCON_COUNT (0)
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/* @brief IOMUXC availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
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/* @brief IOMUXC_GPR availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
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/* @brief IOMUXC_LPSR availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
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/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
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/* @brief IOMUXC_SNVS availability on the SoC. */
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#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
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/* @brief IOPCTL availability on the SoC. */
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#define FSL_FEATURE_SOC_IOPCTL_COUNT (0)
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/* @brief IPWM availability on the SoC. */
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#define FSL_FEATURE_SOC_IPWM_COUNT (0)
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/* @brief IRQ availability on the SoC. */
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#define FSL_FEATURE_SOC_IRQ_COUNT (0)
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/* @brief IUART availability on the SoC. */
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#define FSL_FEATURE_SOC_IUART_COUNT (0)
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/* @brief KBI availability on the SoC. */
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#define FSL_FEATURE_SOC_KBI_COUNT (0)
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/* @brief KPP availability on the SoC. */
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#define FSL_FEATURE_SOC_KPP_COUNT (1)
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/* @brief L2CACHEC availability on the SoC. */
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#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
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/* @brief LCD availability on the SoC. */
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#define FSL_FEATURE_SOC_LCD_COUNT (0)
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/* @brief LCDC availability on the SoC. */
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#define FSL_FEATURE_SOC_LCDC_COUNT (0)
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/* @brief LCDIF availability on the SoC. */
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#define FSL_FEATURE_SOC_LCDIF_COUNT (1)
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/* @brief LDO availability on the SoC. */
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#define FSL_FEATURE_SOC_LDO_COUNT (0)
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/* @brief LLWU availability on the SoC. */
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#define FSL_FEATURE_SOC_LLWU_COUNT (0)
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/* @brief LMEM availability on the SoC. */
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#define FSL_FEATURE_SOC_LMEM_COUNT (0)
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/* @brief LPADC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPADC_COUNT (0)
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/* @brief LPCMP availability on the SoC. */
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#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
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/* @brief LPDAC availability on the SoC. */
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#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
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/* @brief LPI2C availability on the SoC. */
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#define FSL_FEATURE_SOC_LPI2C_COUNT (4)
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/* @brief LPIT availability on the SoC. */
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#define FSL_FEATURE_SOC_LPIT_COUNT (0)
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/* @brief LPSCI availability on the SoC. */
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#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
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/* @brief LPSPI availability on the SoC. */
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#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
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/* @brief LPTMR availability on the SoC. */
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#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
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/* @brief LPTPM availability on the SoC. */
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#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
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/* @brief LPUART availability on the SoC. */
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#define FSL_FEATURE_SOC_LPUART_COUNT (8)
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/* @brief LTC availability on the SoC. */
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#define FSL_FEATURE_SOC_LTC_COUNT (0)
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/* @brief MAILBOX availability on the SoC. */
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#define FSL_FEATURE_SOC_MAILBOX_COUNT (0)
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/* @brief MC availability on the SoC. */
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#define FSL_FEATURE_SOC_MC_COUNT (0)
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/* @brief MCG availability on the SoC. */
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#define FSL_FEATURE_SOC_MCG_COUNT (0)
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/* @brief MCGLITE availability on the SoC. */
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#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
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/* @brief MCM availability on the SoC. */
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#define FSL_FEATURE_SOC_MCM_COUNT (0)
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/* @brief MIPI_CSI2 availability on the SoC. */
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#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
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/* @brief MIPI_CSI2RX availability on the SoC. */
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#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0)
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/* @brief MIPI_DSI availability on the SoC. */
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#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
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/* @brief MIPI_DSI_HOST availability on the SoC. */
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#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
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/* @brief MMAU availability on the SoC. */
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#define FSL_FEATURE_SOC_MMAU_COUNT (0)
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/* @brief MMCAU availability on the SoC. */
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#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
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/* @brief MMDC availability on the SoC. */
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#define FSL_FEATURE_SOC_MMDC_COUNT (0)
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/* @brief MMDVSQ availability on the SoC. */
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#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
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/* @brief MPU availability on the SoC. */
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#define FSL_FEATURE_SOC_MPU_COUNT (0)
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/* @brief MRT availability on the SoC. */
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#define FSL_FEATURE_SOC_MRT_COUNT (0)
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/* @brief MSCAN availability on the SoC. */
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#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
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/* @brief MSCM availability on the SoC. */
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#define FSL_FEATURE_SOC_MSCM_COUNT (0)
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/* @brief MTB availability on the SoC. */
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#define FSL_FEATURE_SOC_MTB_COUNT (0)
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/* @brief MTBDWT availability on the SoC. */
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#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
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/* @brief MU availability on the SoC. */
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#define FSL_FEATURE_SOC_MU_COUNT (0)
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/* @brief NFC availability on the SoC. */
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#define FSL_FEATURE_SOC_NFC_COUNT (0)
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/* @brief OCOTP availability on the SoC. */
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#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
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/* @brief OPAMP availability on the SoC. */
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#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
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/* @brief OTPC availability on the SoC. */
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#define FSL_FEATURE_SOC_OTPC_COUNT (0)
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/* @brief OSC availability on the SoC. */
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#define FSL_FEATURE_SOC_OSC_COUNT (0)
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/* @brief OSC32 availability on the SoC. */
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#define FSL_FEATURE_SOC_OSC32_COUNT (0)
|
|
/* @brief OTFAD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
|
|
/* @brief PCC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PCC_COUNT (0)
|
|
/* @brief PCIE_PHY_CMN availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
|
|
/* @brief PCIE_PHY_TRSV availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
|
|
/* @brief PDB availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PDB_COUNT (0)
|
|
/* @brief PGA availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PGA_COUNT (0)
|
|
/* @brief PIMCTL availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PIMCTL_COUNT (0)
|
|
/* @brief PINT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PINT_COUNT (0)
|
|
/* @brief PIT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PIT_COUNT (1)
|
|
/* @brief PMC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PMC_COUNT (0)
|
|
/* @brief PMU availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PMU_COUNT (1)
|
|
/* @brief POWERQUAD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0)
|
|
/* @brief PORT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PORT_COUNT (0)
|
|
/* @brief PROP availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PROP_COUNT (0)
|
|
/* @brief PWM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PWM_COUNT (4)
|
|
/* @brief PWT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PWT_COUNT (0)
|
|
/* @brief PXP availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_PXP_COUNT (1)
|
|
/* @brief QDDKEY availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_QDDKEY_COUNT (0)
|
|
/* @brief QDEC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_QDEC_COUNT (0)
|
|
/* @brief QuadSPI availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
|
|
/* @brief RCM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RCM_COUNT (0)
|
|
/* @brief RDC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RDC_COUNT (0)
|
|
/* @brief RDC_SEMAPHORE availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
|
|
/* @brief RFSYS availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
|
|
/* @brief RFVBAT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
|
|
/* @brief RIT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RIT_COUNT (0)
|
|
/* @brief RNG availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RNG_COUNT (0)
|
|
/* @brief RNGB availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
|
|
/* @brief ROM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_ROM_COUNT (0)
|
|
/* @brief ROMC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_ROMC_COUNT (1)
|
|
/* @brief RSIM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
|
|
/* @brief RSTCTL0 availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0)
|
|
/* @brief RSTCTL1 availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0)
|
|
/* @brief RTC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_RTC_COUNT (0)
|
|
/* @brief SCG availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SCG_COUNT (0)
|
|
/* @brief SCI availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SCI_COUNT (0)
|
|
/* @brief SCT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SCT_COUNT (0)
|
|
/* @brief SDHC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDHC_COUNT (0)
|
|
/* @brief SDIF availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDIF_COUNT (0)
|
|
/* @brief SDIO availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDIO_COUNT (0)
|
|
/* @brief SDMA availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDMA_COUNT (0)
|
|
/* @brief SDMAARM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
|
|
/* @brief SDMABP availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
|
|
/* @brief SDMACORE availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
|
|
/* @brief SDMCORE availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
|
|
/* @brief SDRAM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
|
|
/* @brief SEMA4 availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
|
|
/* @brief SEMA42 availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
|
|
/* @brief SEMC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SEMC_COUNT (1)
|
|
/* @brief SHA availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SHA_COUNT (0)
|
|
/* @brief SIM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SIM_COUNT (0)
|
|
/* @brief SJC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SJC_COUNT (0)
|
|
/* @brief SLCD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
|
|
/* @brief SMARTCARD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
|
|
/* @brief SMC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SMC_COUNT (0)
|
|
/* @brief SNVS availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SNVS_COUNT (1)
|
|
/* @brief SPBA availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SPBA_COUNT (0)
|
|
/* @brief SPDIF availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SPDIF_COUNT (1)
|
|
/* @brief SPI availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SPI_COUNT (0)
|
|
/* @brief SPIFI availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SPIFI_COUNT (0)
|
|
/* @brief SPM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SPM_COUNT (0)
|
|
/* @brief SRC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SRC_COUNT (1)
|
|
/* @brief SYSCON availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SYSCON_COUNT (0)
|
|
/* @brief SYSCTL0 availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0)
|
|
/* @brief SYSCTL1 availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0)
|
|
/* @brief TEMPMON availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
|
|
/* @brief TMR availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TMR_COUNT (4)
|
|
/* @brief TPM availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TPM_COUNT (0)
|
|
/* @brief TRGMUX availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
|
|
/* @brief TRIAMP availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
|
|
/* @brief TRNG availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TRNG_COUNT (1)
|
|
/* @brief TSC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TSC_COUNT (1)
|
|
/* @brief TSI availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TSI_COUNT (0)
|
|
/* @brief TSTMR availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
|
|
/* @brief UART availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_UART_COUNT (0)
|
|
/* @brief USART availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USART_COUNT (0)
|
|
/* @brief USB availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USB_COUNT (0)
|
|
/* @brief USBHS availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBHS_COUNT (2)
|
|
/* @brief USBDCD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
|
|
/* @brief USBFSH availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
|
|
/* @brief USBHSD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
|
|
/* @brief USBHSDCD availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
|
|
/* @brief USBHSH availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
|
|
/* @brief USBNC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
|
|
/* @brief USBPHY availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
|
|
/* @brief USB_HSIC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
|
|
/* @brief USB_OTG availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
|
|
/* @brief USBVREG availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USBVREG_COUNT (0)
|
|
/* @brief USDHC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
|
|
/* @brief UTICK availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_UTICK_COUNT (0)
|
|
/* @brief VIU availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_VIU_COUNT (0)
|
|
/* @brief VREF availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_VREF_COUNT (0)
|
|
/* @brief VFIFO availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_VFIFO_COUNT (0)
|
|
/* @brief WDOG availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_WDOG_COUNT (2)
|
|
/* @brief WKPU availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_WKPU_COUNT (0)
|
|
/* @brief WWDT availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_WWDT_COUNT (0)
|
|
/* @brief XBAR availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
|
|
/* @brief XBARA availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XBARA_COUNT (1)
|
|
/* @brief XBARB availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XBARB_COUNT (2)
|
|
/* @brief XCVR availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
|
|
/* @brief XRDC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
|
|
/* @brief XTALOSC availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
|
|
/* @brief XTALOSC24M availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
|
|
/* @brief ZLL availability on the SoC. */
|
|
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
|
|
|
|
/* ADC module features */
|
|
|
|
/* @brief Remove Hardware Trigger feature. */
|
|
#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0)
|
|
/* @brief Remove ALT Clock selection feature. */
|
|
#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
|
|
|
|
/* AOI module features */
|
|
|
|
/* @brief Maximum value of input mux. */
|
|
#define FSL_FEATURE_AOI_MODULE_INPUTS (4)
|
|
/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
|
|
#define FSL_FEATURE_AOI_EVENT_COUNT (4)
|
|
|
|
/* FLEXCAN module features */
|
|
|
|
/* @brief Message buffer size */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64)
|
|
/* @brief Has doze mode support (register bit field MCR[DOZE]). */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
|
|
/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
|
|
/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1)
|
|
/* @brief Has extended bit timing register (register CBT). */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0)
|
|
/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
|
|
/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */
|
|
#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
|
|
/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
|
|
/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (0)
|
|
/* @brief Has extra MB interrupt or common one. */
|
|
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
|
|
|
|
/* CMP module features */
|
|
|
|
/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
|
|
#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
|
|
/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
|
|
#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
|
|
/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
|
|
#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
|
|
/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
|
|
#define FSL_FEATURE_CMP_HAS_DMA (1)
|
|
/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
|
|
#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
|
|
/* @brief Has DAC Test function in CMP (register DACTEST). */
|
|
#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
|
|
|
|
/* EDMA module features */
|
|
|
|
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
|
|
#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
|
|
/* @brief Total number of DMA channels on all modules. */
|
|
#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
|
|
/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
|
|
#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
|
|
/* @brief Has DMA_Error interrupt vector. */
|
|
#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
|
|
/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
|
|
#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
|
|
|
|
/* DMAMUX module features */
|
|
|
|
/* @brief Number of DMA channels (related to number of register CHCFGn). */
|
|
#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
|
|
/* @brief Total number of DMA channels on all modules. */
|
|
#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32)
|
|
/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
|
|
#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
|
|
/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
|
|
#define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
|
|
|
|
/* ENET module features */
|
|
|
|
/* @brief Support Interrupt Coalesce */
|
|
#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1)
|
|
/* @brief Queue Size. */
|
|
#define FSL_FEATURE_ENET_QUEUE (1)
|
|
/* @brief Has AVB Support. */
|
|
#define FSL_FEATURE_ENET_HAS_AVB (0)
|
|
/* @brief Has Timer Pulse Width control. */
|
|
#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1)
|
|
/* @brief Has Extend MDIO Support. */
|
|
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
|
|
/* @brief Has Additional 1588 Timer Channel Interrupt. */
|
|
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
|
|
|
|
/* FLEXRAM module features */
|
|
|
|
/* @brief Bank size */
|
|
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32 * 1024)
|
|
/* @brief Total Bank numbers */
|
|
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
|
|
|
|
/* FLEXSPI module features */
|
|
|
|
/* @brief FlexSPI AHB buffer count */
|
|
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
|
|
/* @brief FlexSPI has no data learn. */
|
|
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
|
|
|
|
/* GPC module features */
|
|
|
|
/* @brief Has DVFS0 Change Request. */
|
|
#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0)
|
|
/* @brief Has GPC interrupt/event masking. */
|
|
#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0)
|
|
/* @brief Has L2 cache power control. */
|
|
#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0)
|
|
/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */
|
|
#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1)
|
|
/* @brief Has VADC power control. */
|
|
#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0)
|
|
/* @brief Has Display power control. */
|
|
#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0)
|
|
/* @brief Supports IRQ 0-31. */
|
|
#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
|
|
|
|
/* LCDIF module features */
|
|
|
|
/* @brief LCDIF does not support alpha support. */
|
|
#define FSL_FEATURE_LCDIF_HAS_NO_AS (1)
|
|
/* @brief LCDIF does not support output reset pin to LCD panel. */
|
|
#define FSL_FEATURE_LCDIF_HAS_NO_RESET_PIN (1)
|
|
/* @brief LCDIF supports LUT. */
|
|
#define FSL_FEATURE_LCDIF_HAS_LUT (1)
|
|
|
|
/* LPI2C module features */
|
|
|
|
/* @brief Has separate DMA RX and TX requests. */
|
|
#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0)
|
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
|
#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4)
|
|
|
|
/* LPSPI module features */
|
|
|
|
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
|
|
#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16)
|
|
/* @brief Has separate DMA RX and TX requests. */
|
|
#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
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/* LPUART module features */
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/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
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#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
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/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
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/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPUART_HAS_FIFO (1)
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/* @brief Has 32-bit register MODIR */
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#define FSL_FEATURE_LPUART_HAS_MODIR (1)
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/* @brief Hardware flow control (RTS, CTS) is supported. */
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#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
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/* @brief Infrared (modulation) is supported. */
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#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
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/* @brief 2 bits long stop bit is available. */
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#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
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/* @brief If 10-bit mode is supported. */
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#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
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/* @brief If 7-bit mode is supported. */
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#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
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/* @brief Baud rate fine adjustment is available. */
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#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
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/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
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/* @brief Baud rate oversampling is available. */
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#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
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/* @brief Baud rate oversampling is available. */
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#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
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/* @brief Peripheral type. */
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#define FSL_FEATURE_LPUART_IS_SCI (1)
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/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
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#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
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/* @brief Maximal data width without parity bit. */
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#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
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/* @brief Maximal data width with parity bit. */
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#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
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/* @brief Supports two match addresses to filter incoming frames. */
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#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
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/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
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/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
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#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
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/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
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#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
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/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
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#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
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/* @brief Has improved smart card (ISO7816 protocol) support. */
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#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
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/* @brief Has local operation network (CEA709.1-B protocol) support. */
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#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
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/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
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#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
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/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
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#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
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/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
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#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
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/* @brief Has separate DMA RX and TX requests. */
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#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
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/* @brief Has separate RX and TX interrupts. */
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#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
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/* @brief Has LPAURT_PARAM. */
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#define FSL_FEATURE_LPUART_HAS_PARAM (1)
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/* @brief Has LPUART_VERID. */
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#define FSL_FEATURE_LPUART_HAS_VERID (1)
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/* @brief Has LPUART_GLOBAL. */
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#define FSL_FEATURE_LPUART_HAS_GLOBAL (1)
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/* @brief Has LPUART_PINCFG. */
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#define FSL_FEATURE_LPUART_HAS_PINCFG (1)
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/* interrupt module features */
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/* @brief Lowest interrupt request number. */
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#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
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/* @brief Highest interrupt request number. */
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#define FSL_FEATURE_INTERRUPT_IRQ_MAX (159)
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/* OCOTP module features */
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/* No feature definitions */
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/* PIT module features */
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/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
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#define FSL_FEATURE_PIT_TIMER_COUNT (4)
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/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
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#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
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/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
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#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
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/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
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#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
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/* @brief Has timer enable control. */
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#define FSL_FEATURE_PIT_HAS_MDIS (1)
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/* PMU module features */
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/* @brief PMU supports lower power control. */
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#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0)
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/* PWM module features */
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/* @brief Number of each EflexPWM module channels (outputs). */
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#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
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/* @brief Number of EflexPWM module A channels (outputs). */
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#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
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/* @brief Number of EflexPWM module B channels (outputs). */
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#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
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/* @brief Number of EflexPWM module X channels (outputs). */
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#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
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/* @brief Number of each EflexPWM module compare channels interrupts. */
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#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
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/* @brief Number of each EflexPWM module reload channels interrupts. */
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#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
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/* @brief Number of each EflexPWM module capture channels interrupts. */
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#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
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/* @brief Number of each EflexPWM module reload error channels interrupts. */
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#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
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/* @brief Number of each EflexPWM module fault channels interrupts. */
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#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
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/* @brief Number of submodules in each EflexPWM module. */
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#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
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/* PXP module features */
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/* @brief PXP module has dither engine. */
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#define FSL_FEATURE_PXP_HAS_DITHER (0)
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/* @brief PXP module supports repeat run */
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#define FSL_FEATURE_PXP_HAS_EN_REPEAT (1)
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/* @brief PXP doesn't have CSC */
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#define FSL_FEATURE_PXP_HAS_NO_CSC2 (1)
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/* @brief PXP doesn't have LUT */
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#define FSL_FEATURE_PXP_HAS_NO_LUT (1)
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/* RTWDOG module features */
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/* @brief Watchdog is available. */
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#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1)
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/* @brief RTWDOG_CNT can be 32-bit written. */
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#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1)
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/* SAI module features */
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/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
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#define FSL_FEATURE_SAI_FIFO_COUNT (32)
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/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
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#define FSL_FEATURE_SAI_CHANNEL_COUNT (4)
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/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
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#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
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/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
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#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
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/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
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#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
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/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
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#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
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/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
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#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
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/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
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#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
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/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
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#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
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/* @brief Interrupt source number */
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#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
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/* @brief Has register of MCR. */
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#define FSL_FEATURE_SAI_HAS_MCR (0)
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/* @brief Has register of MDR */
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#define FSL_FEATURE_SAI_HAS_MDR (0)
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/* SNVS module features */
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/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
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#define FSL_FEATURE_SNVS_HAS_SRTC (1)
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/* SRC module features */
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/* @brief There is MASK_WDOG3_RST bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1)
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/* @brief There is MIX_RST_STRCH bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0)
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/* @brief There is DBG_RST_MSK_PG bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1)
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/* @brief There is WDOG3_RST_OPTN bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0)
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/* @brief There is CORES_DBG_RST bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0)
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/* @brief There is MTSR bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0)
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/* @brief There is CORE0_DBG_RST bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1)
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/* @brief There is CORE0_RST bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
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/* @brief There is LOCKUP_RST bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1)
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/* @brief There is SWRC bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
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/* @brief There is EIM_RST bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0)
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/* @brief There is LUEN bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0)
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/* @brief There is no WRBC bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1)
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/* @brief There is no WRE bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1)
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/* @brief There is SISR register. */
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#define FSL_FEATURE_SRC_HAS_SISR (0)
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/* @brief There is RESET_OUT bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
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/* @brief There is WDOG3_RST_B bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
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/* @brief There is SW bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
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/* @brief There is IPP_USER_RESET_B bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1)
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/* @brief There is SNVS bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0)
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/* @brief There is CSU_RESET_B bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1)
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/* @brief There is LOCKUP bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0)
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/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1)
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/* @brief There is POR bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_POR (0)
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/* @brief There is IPP_RESET_B bit in SRSR register. */
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#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1)
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/* @brief There is no WBI bit in SCR register. */
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#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1)
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/* SCB module features */
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/* @brief L1 ICACHE line size in byte. */
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#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32)
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/* @brief L1 DCACHE line size in byte. */
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#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32)
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/* TRNG module features */
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/* @brief TRNG has no TRNG_ACC bitfield. */
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#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
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/* USBHS module features */
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/* @brief EHCI module instance count */
|
|
#define FSL_FEATURE_USBHS_EHCI_COUNT (2)
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|
/* @brief Number of endpoints supported */
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|
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
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/* USDHC module features */
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|
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/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
|
|
#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0)
|
|
/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */
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|
#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0)
|
|
/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */
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|
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
|
|
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
|
|
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
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|
|
/* XBARA module features */
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|
|
|
/* @brief DMA_CH_MUX_REQ_30. */
|
|
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30 (1)
|
|
/* @brief DMA_CH_MUX_REQ_31. */
|
|
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31 (1)
|
|
/* @brief DMA_CH_MUX_REQ_94. */
|
|
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94 (1)
|
|
/* @brief DMA_CH_MUX_REQ_95. */
|
|
#define FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95 (1)
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#endif /* _MIMXRT1052_FEATURES_H_ */
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